From c8031934fba1214fde6d8b6be134d38a0389ded0 Mon Sep 17 00:00:00 2001 From: YuhangQ Date: Thu, 23 Feb 2023 05:42:34 +0000 Subject: [PATCH] =?UTF-8?q?=E8=A7=A3=E5=86=B3=20stuck=20=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- atpg | Bin 66352 -> 65200 bytes circuit.cpp | 5 +- circuit.h | 2 +- ls.cpp | 62 +- output.txt | 9702 +++++++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 9743 insertions(+), 28 deletions(-) create mode 100644 output.txt diff --git a/atpg b/atpg index bcc3133557e48c38e5c7307879ae4bed54b15caf..89417e76218e00e4710421ea9352942531462445 100755 GIT binary patch literal 65200 zcmeFa33yaR)<1kZ3p86g2xweJT8%S_ASNuD1{@QTklWIMjDY4Hmk>iBc?}SgZix#T z?QZ0HX^n~_GddcVnPJpXoKa+46SjaW;)W~exZE}_U`+xr5 z_jq~IRduTB)TvXaPMtbc_i|OSZ)%dmq1jKe_DhYa{2U3%R~hyDR0Ki3mZuHD?{S)2 z>xXoTfXV!P86a0a+mpJ7P6ba!$a)!!^b#H;!I~Y~6f$JJzMhODWsV(c=`ziFsf@b$ zgU2m?X?ywM+*`TDcn!&e0{nzmDgc0IC-_41yS z<@28J9;PdP+M&%)(#XF&#m}Ch8cxj)d)BK_^?HUyvU$x8*#@7PANlA0C+(G~db9o@ z@$?Me;XvWBL%Y3Sp&t42V;?o_+F7c-zQ$p#;=diL=CxDmYA-x>{3&&FPp+$77-%}V zDeu&iPaQv|anYEuf&|j##viMfOrNb`SlS3vY}AsPW!lEayx}UJ#z(T;!{H&Pme>4WduK3@0ydY&Cm#&fWOo5x3&7k1rL8V zcUHrb{U(-nJiqmhW9rv7gndW5zS;LOvU`2b1G2+<$$1lv_XZ!)NBO^iu-?k==mSpx zo$jstoqgb+3L1MWUj#<=2A|glJ&r!gAJqr^Z++17yFTby+XwvdKJe7`0bkw+{OvyI zZ11D|ReiwE=>yLleU!hqkMX*+4?dra3DVoROzQ)GtPgsw?W6qYKFUw(gU+pez>Pk} z>#IKKzq1ech(6$F^dbL?`|4L8@Z0+6@1Z{Er#^Axujezl5B%r$LH}R+fG_ByU+zBm z3^D1Ip3!~4f6)j2dqMy4Jv)W;YVhYcEkj%RoXl)iW$pt#gs)QTuv@{e20?^psCCwc zA5`$os(iC5zXR~&sikk0fc^?TQI*$KyJZTlRaDGhuxMdLqrbAjUs0h|cxRPX%&l&y zo?qMOuWp!CT3EMeVfC!a3+t+7Uhg@-o<41+|FnvVs-~vg+}yDjRyNjF0cS()!uj5+ znf~0|s+!7%3V%aot-sM*RXnp2KgFk2Em}}t*-%|vHmypl`1SOe{!{A~RaMqi7v&aT z0>DiF*qn+Ae@(-p#T9kc3+MZ5DykbA7B$3+|GN!(DoQIV8yjoqFDyQ5+RX9jEgSVn zYHJsPvhR~xJfW(ty0W1dIb$oliyHaouk?c(zn*nAfa6u|dFX9*<$_*O$aeD3LIp}! z7mXF&n_E|Q$pWI8^>3lc9Vc6yS6f$oVPIab4T9!Hjn$$R4$Ooq|E2ZSV0qr$MHP!{ z=Tc5*YYnD2fm1Y4fZ7Fj+tiD)uTCXLVtO3<{>s zs+g5iQ9SdsinGvMAES=(oH?OlR&GUcu^ifkmEKD_yRdR@MP(hN5E&5W%8Cmy5f)ZdRr;%HfDEWkO)Oef+2|(#(ut1Cokp7sNqZ(ScSWFbmw|_BN%0NOd!VmfB zF`z=)3#Cf>k)zsGx({LPQ~0T(svz_J>f*D=DItUn)j~QYUH=Kj1p%ro@E(F@BTW$a z9%3ORCpWi3=P+J)slU3hY}zGpVyYL;wdcd^g^O#EI;*-duz>Ok#aMMwMODp374skv z0Mugv@XsRz325GGtT7^MLG^+Ki!NauPBPHeRO?3qn;I?~T#6P{)-Kc<8!8vhRfXo& zau!@xt)Xt!f_esx)qatxzf?obM*rNZQKPs8I+e-!RY1j5E>l$!UQ$?CF>XwbR#;wM zFvVMuJ7(ONJgvm%odN(d#*fMEk<3jj>giT=tS2F_drr4n6B6@eykhK_@$p!0S9Dxg zbnF;a4`o3Zm+K_#wo>rNf2r7A$yk5HlaWfrKc_Z88z|C*4Z`1GctRLY!(X!I()x=q z6(M5|SPK2bKgJz^u&n&Y6!&os?G4y6ww+e?^GgRYwHq)#4z##g<+mc;^zuWKkpdcbeFOO~(c0bilu z^*!KsDtJ>5_#Fz~+ynkw1z*+!{(A*)=>fl6!B_Tx|53qPd%*8gaOYOp51S8my6q(i z2lIt*K&CWpa{@eZU$!*?ev(}n;r0Z$Vx`F4nE+QqBH&g6d~5=qbVa8Fu&f05D%CFt zq3~bWS(_8!^l8|SZC|sz#|9#_?R~<GlK{uWia+%U zaL!x%X-a@&ixGdC6X0yyewHP`IX3pwk^ontFS1r9!0j<+Mr#5b6DIzwN`McHL$NPP zfJ1@ApS20_!EvajwI#qYq2tfy1bA8;3ZGK~+?4>|o&ZlzfbUFz4^4nu3GiVF@I47| z`qAv?KmvS(4P>a~ki0xR0q#tIE7z^aO;3PlB$UrcfGgLs$aN>ck4h+?l>k3F0iKfp zw|&~o&P#y*ETMdU0{qwnxSjwXnE)?KfV&gm3FYe(;F$^V zrUdwj3Gn6w_|FsI%M#$fNPxE_z_SzJD-+Ox^Mjwp-yge^P9#9^BwuFS;F@ zaMFXCwl{X-Cj;CoT?~UFS zPt!o&8@(}}reVA{dUZTaBW`c>;&_^d@ZM-;JWT_5Z}eC3G!5Uq(SmrI2JhZzZahsx zcW?B#c$x<8-ssSHI!&Y<@w7{%zc^&~mxe6*A5YVOMgQYzZmiJ%c$$VR`X5izfJOh~ zX&SERe>_ct75$H=X{e(A@iYxo^go`aVT%68(=J&68y}!F7imJCk)C~j_jGBGba9XL z={?dDdZbV8kv_3U`e!}TBYLEV^hl@nNPl-k^Zbl`lBA{cYCB?>ydt;M|xwA z^iw_3kM>CarAPV?J<`ALk-nuzI?^K@?vY;7BOU0GUeF_5-6MT|kM!&w>CztQ;vVVK zd!#4yNT1vzePWOF&w8Xs^hgiskxuQA{_f9e{H;z%wKWy0N@#LpqjeeLy0P2Zh78>- zgl3K7kS%s_FU@rl(R6I?g1 z$aGuZVQTBf4r>C6G3PV4o%0Wsb2M^V1O^f@1Q=K|Uk}Ip$LZ!NBFEZC+Kk zmuOG(Qjs3q=(H|Ez0OZq_yB5R)Z@bPE99_G0nIGe^X*LK}eQEeZSLj;w)eE_EdLxk3QgeJJ2Q1Ai zWC7Cd*jAU_G<2MmH~?lfcS70u4Z5M`I0CLKFV#y`JwBE6acjRdnQ*$H#Y) z1Y#%~^W(suOJD|oS#jV{0h|O_dK~s0n*<}mLHK$Pl>?irn3Teb!y7=xlt9my2Vt?w{&B93gcippjiS+{TNBjzEhRN)U>|ZFIy4)$K>2e zddQF`&|d zD4&Z_IFS|>nWX2o1!GCB@J%q`pSkg)6CJwowUvST&xjE`7O}rmcIUZvqd)7}sU5z^ z{Vf1}so(E2E}HX9K2dcP)_^drBiM{zO=~_w?-1haM8Y*RxJm|VWw2QW+Ywk#k`Lz1 zt%&PJkV5^8P+gJXw_y6k^xy{vd=aSr6)5L5QZnc1u7#WRRF;|NbuE0A>9%>Ux-EJn zNG*tVsUb-W@L33uxemj1!eT%o6DlqdWey;Nk8aL(KEuMk$lT0y)ZoyOtyor556H3t z8Os_$Ih?7VAfqGbWIcA(2-YKt3U9~?=^{f^Scxc@)*)zPaYO~D5CvZpL&yno*frFY zoH7-Q%2D0&d`%VwoYWRC%p%$y)<;em{vKNq^y>Ek@QtnJwpjyNJTl=Q384L75yMQU zK57_roA zwgDjQVt{<+`Q`;07~u@CCCBOeSRi=Z8>?Ot$)<*eyF%7}JFnMY8D>m@J;?)OC|T<)hF zoPGm>&UDP9{Lp9q5Nb7I-k!w;%^lWG(wLV4X#N+FuD-fSI#x*iTUUcn;X6lijIa>wo*0&rd^Yo{L zZhG%rJu+e&qS3F>SbYDK`9ib37V>{;wy6pPwcJt}E$kqa*X6wPzpS=T7-T25q7~SdzxE1{Z?3xQ&H>D0h z+HpSW#@lE8=wf6ldY~hXe+q|5M~Ra%B=nm#0{q|%lFAA8b%K7#%CQ7(QObF9loqFB|;EOrWzY2#dL+KSA=(YA1X zuz)tq;5XPktP*FJxz-ep<+u;V5b6{v+(a9bOrp6C3TUgO1iEnc&qZhS6q zd4rpvHOri+wG_2{o-YIMLwLVl7}rf+^w;`tkvBKf=?c#f8h%4Yg21?S{$ktI8zdP8Z%3G3Qx z{-zA7!&}wg9DGf9i+=KOq|FjB$*Ym0?bT*pOjaPEF6&ZDz!wZb>bc7kY@viZT&+uouJBJrEUkM^Z z^}r_8-!8xIGXr4VerpaIEbvSn9eAt2JZE%n8(`sW;8}rDGTJJ%GZ&B|!Al|_KauVA z>-c>(lEkn5iPswQiFv;*` zp*d4OPmCp)5J5X;>r{Ea>{GqcEu`iw8B%(HY)Fb~LF z;d?2MfaCzuBp^2d;`7|oDiUENkelZT<|7^W8RC;Y!DhyXuEno5$y~*Pp?zoyGWoZQ zy4Z8lXR(-RvTSafc{A%5nL(CDx!3<&m9tV<%9lCWoRyhZYV1VbUONx-^W$Bx5LZgv z=Oo~M5pc|QQj9g-yqTTxVIv~3XW1C6KZ3kG(e{uBYc=h0p|B$p?n4=@1`i>yrh-fyjtNImOZq34m0!IMUZZc37M6Fm9V0fC^L zTne^51^_{=BTh#T9b)d*>Ujg1}y%3UM#p=vK_@=jXQj0{)EmC9nr%0auNN!e?z z&?l^Jp071uJ{I}sWtIgtbGL^r?{>Hm_V3ptDX*aj#NlP~0S$v0KB(VPsEE*;DabK_ zK!*f8=O3+`IeK`XE7T6SZcc}Mv;m8;8Hl`|mtEmM6AmlI^IYK7QZozA7+2^P;s|a` zFKAu@LckOD@eT!8eNF8|XBK;|>=6*3Fohu_C8SRhe1Z=Z}3VgAJlrM z^$DBubT)j-IuvSfB<|68mYGnj8Dd!A?t|8Jg*VbQ1Hv%D%J7$uNj3|c1=>S*Op$qPt`~(AQ;_xx#m_U?e`xw*BjAwn9y_6>6GEsdi<{8D;GdTdV&= z)2xINA*NYYuhZ;oTiBInnmEr@z2 zJ-U*R&|uaz#>goqvZ(XCp7;CBwX%<@2o5O3^mDBOQahtkN?0r3WGCg{5ax!=tu`;z-@%!J%Kh1_H6U^DCrk5{ha0~n3?*3cEc zmK?i!0~fz;MiJPIY2l4rSue)JdSL)IZy&;6W%K8m3?PzuzhZ+ONMg8+jjY)8cey^4 zg9J|Y$dj4P$la8m4!j|;0&t?0TT5BhcsC}GJtI!p_v?)XAC9o*LaS~r2R7?m8@ zfwNOhjwoH9lusx?vfXVB9R%8RL0di~dsb#SWoHx)XO*57BuGsy=6C1KtPgd>`CKm= zKw~aw11Hrwiu;Vwuj>(%&<#iDwUlT2_ST{gLitz=KLXw8$!0(}msnLdR;YA~@FEEZ z5`I3w4sC;LsPx*4ZM2vlk*AiSvd=gunONsUC!$bJaXCfTAokX{fymg33~9G?r{m)f ze>@#;fsXZYI`V+g3q7an##`2ItgO+qgvX5DRJf^hN!1z*JNvns{hVa449)ZdzE9JD z{AckpS^U~wi$9G0eDrrh@50UTI6A6DH*`;K1TxEm&d4q6`sl-8upR$vLc9&}7V=Np zZ**>XjaY&iw;kBKS#BI6SZ*9lU!+b>(0afi9Ks+I1yRY)#a zbRdcZ;d`h&6fof$H&$|J4 z=LJe$45-2`b*S?F`MNo%$oQ1oMFaj{xjxa}#4Lj?=h+(A#KDD$@v-$Vq(k6Hz~9C? z&1@{iNVKIuTWS z_#2=N@@OJ$r}5?1_d_p`&F18-u(-U&HeY1Cu)lCdIIUF?g%l3v9^+xl(BYrH#_YNHf66@oRA4C z&;tSsG&`1|?Z|@eKKFckrL;Yk(eHLpGZtYNnt?Lbdq}D!N0&>EE|(mv3ZkPJqH<>k z)*C$RNV%9t*5M?C>y0biDRLlSa*-e-;AW+aIS%P&zi!e6u{bD-Lt=}853Z@KGtJ4T zaYfP{!3B^ONMLvi)>uj3FaJaOE@3@M-xG?y9IxX=I>RWN?{pC%{9|HC)E&_kXgFcr zNT*76Ti?LsiasW?@-Z-CFO6PW?>otpZartW)m%cyz2Jjj0viqYi-9JvFrNk*e!u{% zmN-k3tK}EEG5QTELS*%eehi6}a@f`0#cWUPn9yhr*VjCI;&$~doY`wL35zlYYV^yZ zAuk$ALUDUtUIw~(pa@TOutYoZbBRO(&WQ<+40(hcmd*Fy3Ag$X6wdxJSu~^P?63lJF=@x;{Ga~ zy^!;^7-g66j6b*$tIhC@AXT&K-(fG8Y{lWtcD$;TC6MT5KGSeOr8eTvW6>C3i+&zw8-lc3W|Js&-e03-Sx z<-}FI6;6A{R^8a^x~bil{iz<_f*leIP3kM`dY$K?e6Awrjp3Qrb)w90c)8nk z$NK1*$YVKkGMuEuMGfM#GDRsYcby?A=YJPiP!^6F-Br@AM~)Gr)cGekor2{UuDjlX z%_8_c3w|T`oy{|NsiBmo`MMW7Z0xXVuwZpIW+uo(;yyP93_^c;K@Gi47|Me4#I=JD zkwyLxu)eFhXwSRWrY-LI$1$vsK#Z@hn~Sq>2#}+XDuFBSBaX5+`)i*O)!V;G_6EPj zneDTBa2u{Se9(_0Y@UOoymQjUk(^_z&jW?D29kht4TyJZjdhhxja908Iu)jrp- z7X=)**!MyY3~>zeNfX#XU|y7x`e(U|2m zI)rfV(Os<7Hi*iIxZ>A-VQ^1 z=NsTb$+~d} zWdiSblOhNhoxI8a-74m%G6VU5T`klH_9IHJBfZM?U%MFk zW99pHYixYfy5#%NHYwlxkk=*Ot~Dh&aGj+f%w69yud6ZWI}UH~sw}7L+CkW0nI*6> zhSZdS-l~+Vb;ssk+V>rF^V+p!si~RyqZ14W9CnKJRW~1#`M0)-V*Ri#>BbuWEM7TfDePc5AxPZ;;Q{!3hK z!}SN4&9&S9V!mC|{>@0(h@-Qgt=*RX3r)-3y4Q8m=6SAD+8Y{t<}_^23v;}lcK_MZ zem2vaFB^-yPkPlroCvp|m11-FGVDep>_%~Tn?KWM-ndqhrx#7VKxdYxKK;tZ5-y{Yr|Ut$0^cHLAB4Z zjhOr>=30ISe@DWdl+sq5yY0-X6xH*XdP~m!DP3Fy%nB*fS-Au+`b+mB=G78MeE#X)o zO|KHUU_cWxb=9qP(Z2wbF|gEpSTs>3E@FDk8`%%flaUNqSy&zyf|KTm(x zoz!{KK8M=OV;lRo>!Yp}^d?`+(SYt3`#tQ?bgyv`Td^{nH{mVpZ9eny z08VD`>A1GJ3rJo{;3^e^Blmg(AlxX(0mx_G#x`=>&WsHH1Lr2DcbR~j%S0gb7c>Dm zrJH|Siy+SL;UyhKsTv?!K}QPrWel-4i;!TZ8Gt?k#u70VJWH{Yp3Q;3cWrsZMb0jH z(br<0@EPf=`poCCT-W^ag;;EQWc*)<(cAt}GWU>YZ=r3wA2*BH9jhdsWVfumc#@s6 zvg1j1&N@mY;c5|`v<4xGID1NW_g~Qpm|UF8HhGI!>l{S6#p?zv@(dwoMn>m(gB?!m zrOm8c3}4crzt*2*gwwh;Uhnh3d${qOhr)b1#C0de z0E`cWLt0F*6V_8H|BcLeSI;FtQL+147=i~`-io@GT*sA?mLk(#jGGY0%QIEXdX_*f-X#k@l#hf%&laN1JY8O7nZUEwj1z2?iuYyLC!szPzWZk=mIyKBw1<|~Fl zgJr9HiXM@7TfFcaWw05Z zHO=uw9#E&q>Qp5HZDcIZBzo3pM)NEPpQ$Qf$d{RTS;5Ida14_s9dJq!;aLh!+L$Ko z><{fJ?P?ShqloZLSmo#m6{n{DznBylflBNhu>!Zl<8w$|pufw*8d z-0ftK7w^i5Gd$kN!r>sf8+Ah=*>;#B<{sRd=3yAQ+#&f23<8t9XF?BA{2Yw%s17W8 zM80;1ow=1Cg`aC2fb1{ed%y?w)7c4l+>U-y475BKczPon4T%>563^>1fWD_|?pga> zfN~ODj47>nY%X2K;#I>q4-0}1HY0@zv9yWh?)w%kR1Ly~-PJ5)4u4j!8h#B*trDfO zf76O^QxRrN^d%NGZ_jK4**pa}Qs~KqbGvj>EB*iW>6-nnUtI9*vw*o9WX~u`KJ#8V zfC<7$DP%)@=)tbRc^NKy2mU)ckMlNePf>0*V`!jB{GOhQ17>)e|AZgG23l>lV9yEhJ0Bp!nc94*eHaTpp1%@j4jhhSClu+!v+}h+HwOW?-}E=eZK3KjW}mnK^2Zm?a<=J%+dMB z*JYmLA6Z~79-X@lHx5^H1& zqu+#^h2^erJ~V|bQ#x)@x>+*(Fdaj9y{AUw3oGiCVGM8$UP-Zj(atJenxK#KK#j$E z*9Y-4!SmXP%6{{g*HZdY0w6+obmDIS--W7F9aN)&gBr|G_CzdI(0Gejyf`12{%4M{e(D`^N!Ei}XkLBR)BI@Y*qUvNOxnxjtSR1=q54 z17z6e`VcTTya{u-JW`=pr?I*`KIf287NW$#Bh=lbm~&S*T|u5sX8qU}2d9 zGommDKhtuf8#!R+MfGqRG(m;=uax?OuYy6>lmV@`YBqYJ3=o)WrV~5;skS;=GlxYc zt*Jra3VG0^&%X93vrrp|$Sk>zEX_xh>xf`C zpAA|)NU*yW9fN6WmxFZR2yTTGgbVQH6>-c!5x`MHzAqy6OoBLszYrshV?R`dJoMKM zzOvk(w;Q@nAM(A%JEHxc!5S?56Xw~rN7I-(I{Fr@ z(k}Z$_#0>Ewt0=O#S6va^vsDGKJ!nU7~cKw_(uJy2{B*tpD6soGYUM`O~6xNmWua? zK8IDz(y(Uq{qO3d?q>x(`F>G>{^J6pc(gSKHPlNeVljG4A0^#C$-)ih^L*fS`CgS< zZJcI{14hyp{RJu}?(gE~rQ%M<3@oQOO^0i9IQOr@-!ZRa3RX;94G4g=^UHi@weIu$ z!xefQ>Pq-IO3l%kSgoAapvPgfuWSEwq+@Gvrvt5mQWV8L*DQuuo?oVCujf6$V5g($ zssiI3Z~KSIokQa5D@&bej)xrYMhPznvMz-k75rx`@L}f+(o=sxH*cZ-k~Ua)4x?3R zSV68c2jb*0&-OZmg>J&73bo_>OFl|s#~CJPtrLX({!}?@n-U4!MXg@V3u$H*=kCkh*Lgyh{P~Q{ zJ{+#%?n1ELA?`02FJdSg&w#6EFC50wfW=FAd2k)B#fj{T_=p9u>7GNb&~###Z~f@T zqfG#JK4`BSe-JbnUzcWo(1+Y@xaq5}#2(Ax-TyUD#HX3V zztv4APO!iA(q983>+^kNbh=ykgAUmu~zPV_M9N2(t z+MF?3cqFAq6a7e*E@C6Bqq;h`QMEr7_OT?;CRfl8(PU}bcG(B?>^(5bF$X*JY`kJG zIsy~g*Vf@nWN1&ggR2LAqTzY)Oy{s$?xux7YvT{XAbB{;hUJ4 z<9h;l4@Ht>uI7GBH=AjeuqMo=-pfBq8G>Ep%l_EPc#Qj6vBtobmY+y5p0$1@uAvk+ z+aj);Lc-8}){Ra<19__6N)52X z)&Tb_4IswbI*t?4d_rmfi3S?r4xf1uX5cg(F7;+G#0N7UQz&~gCzIIV{25T`!FiN| z1(C%xzzvaB@Cb9YxW!9(dOAicFIugqI+z{}zi~ zP{C_%Y2y0ZZr+M(V_*4MnKuqXUY1FDiQGbt>X9Wae9Pc7+<(Cv$Sd)RZfo>uXxbw4 zZ$w#)?PIt^YTon4c4^-4{tAmv_)^ttogng8cK*L2vJI6BeqC@bX!2tTNSp#AKx${1 z7=Nx;eaLI~_3DSEwUIBYeNS3jAsJkOf~TKZp=l^kmJ#S@jQAxIy7_zNKrlI8(4NJu z48L?On(4-F1Kxnys{m{x5KiosuIyVV&aUj)tM%Xk96i)=`($9T?!;}W%b8GD0)_s> z0O6Gjaa+pz6BxnkhLK|ETwJ&pB;g7ZR_k(J5OsxaKqK-K6P+xpTrhBxf)L1Vq_hXUS5!1D1j z_BU#+0!MHS(Ptj%#pPr#W)}Pm5&9WkD>a8_`aG|@LOxdJtM$BohVp#(@-;u+8W{fy zE8tks=#Zaly6$20z^3SEN{BBq1$`0=mCwk}-~ffW@L*99-8BQNfUzp|zmmJyudA87{B*rboV=*kK81YTCzNAa( zbyxTnGRfGEvb=pLOc;uoDewsi5i(6#3O|CzC`(5r%91O@EBBNq5@ibzZsvJC>-<&T zj+9J}129EzV0CF^Mc?AS*=UF5FILExqxyh$3P}52S9x3Xb(WOGC`#1Sir&q7N_`mZ z(Z7qGo1joP^z_aaT-iL`Kg_z|L5#wi_=)cqthfKtwOu<0x_GspKo|IU5U<3UE^{kpqB$p7B`x(&eozi?l42+&$9ABeNfx*c)hyX1Y*-Cex3 zPC$35_$QJ3ad*4qAMT45%y_66U^m#RT3{m~Zw*U)(>C{<(SR zW#auhu3BnM!uxB&Rp;%PO68=LMi%16=2Yl!WvBuiS4B8m`yvm)A${1dL;JD@auPGM?PZ zo4mSwX(Qcd{v5_iO8gUNyu};5Dg#cwW^`99JospZ_$&b5<-=D1#7ktY<=G6m0o@_3k!CkYYkTO?qf8R`Wa&cJry4#^-75=Op5{b z6E3%tmH;&IYjVNA?>>&*>l>+CyR^WnuQuTyB`b> zhIlLYBKlDAsUoE4w=2$Yh=n407Bp^Lzt~H@pK91sKJaeqYfvjm zMH`CTuBHMwq$x%>@kR*ROB_~ywd@$YqRU)|_|B4b@Xz+ZZj3JLHrZ%rQ@w$^|LXl4 zv97iNlUP^LIvDc3_iy&BA}4>``!_|vCC>|bdH?1=(w`ro^+f%7A=CeB_me~H>;L?H z`xpKM{aKD5wd`2uAs*MC51~<+vEKTJAYg~}PlR35UFy$n-yg&`LVf09=(2=4s$&vG ziZXLH;ZO5A-lJsmTnfUE!zsuf?6fakp@$KH8pZ)yTz*|^M&&nu=k{NO-vRz={GPt} zcp>L_KjvxH)P`wp{gs`1c#kXm8zlE_$PAp$sR~OO)(GCMc8KG`y_~H$a>(&{4!W+P zyL-yA(I|t0K73~;Ys#jSJgAGgINS)Xci@W%fgm?);b%oXx~8ER`Mr!Z)`6=QA9MWt zkCecogs;50!nzTST*qu7GBb^M*IPj4`YXye9nlzDyoNsa6FC^2rW7Q5QtO}4Zicy z&-2mGv7lLxT#hc{V5*Kn5bxnjs3W=m55!z+inV22)v9Fw#5si+f@l;5p~U;W{v5Kt z08OIzQ8TeWIP}7niZ`CN;+rwi2_g@ah{G_vc)r_OOZXEKjuYel%kb{T9U_^Ja)KY! z*;f-kUjtPPK^#Ql6}dxJzk3xss5PS(qHeq%z6UJo;SdL$M6|ulu*a+eE zZa?IyI0JAow+{n-Pm^f!Iu!{_YHa(qL+2+vrJe$osa5Mt;(f_+>sKVA?$T-XMf^nBrGFJB=D3@SA~i3XLN8ZW|23g1R1 zfYu#om?|h*ja*v*Mqq`&*@K*a1WFmO$NuVFc|4JZ%EcF>9>}B{-G^f@H>abqJ7L)f zWoDruUBr0b*}A!vLY%sx1fXqn+k`|_-Ap~wD>w4_n1bhG-Er z*oc{L@lgH%8s=kv&=;6q(vd_~7K({1v&r%~V%B1IGm^RoZHsn^CD;c0OwkZg7i;7N z4mU>M`Vi!bgOlBs2erl5Hgp5iX1`^yC%D-niMfm|h-2|d5Ndq4={nIE-klZbjfQz@jtFqAR2v>l8`e3IKb# zU1hkk@l6hUyofx`CG+-_bgmxsfW3=bjm?+m!OZ>w^;}QSEYu^n3tXHq#(UObLKZNE z&a(CurMpvIVf+398*I)y!G90DDvyjLB|EG~?%>Sxw*d6$F%oo_0J%b!LIT;D7E}|R zfU5=Mwj#-g?k99bd@rQlzPxAo_mim)sJF~-7nQxnE^qcb-mAZDMYY8NM4AzCiT6l2 z0D=*b2`7Ri@qtUe9LcXqull|HCD!R+yVCEVIR_~npQnfnSvmwSZs3D36egTBVwK&E z3GlRl7&~HHT~BWnFO=dufN%3fCOmU2{6uZQOCMXa=-}mZ0Pi52?Gauh;7fJ_o(rB> zEecK-3a(bC+9TSAhWX$_&CLk-ZF0Ch)z@LbnmlrEHF9VfI8zt_v>Yp1YT&Zy)3`R( zrJwojnet&<3jSCl$YCqgd%jYLNb?=J2Jsk;9pB{_$Z8s;(jHv ztSJhfB;n-#b4LMwl7fHwom~8yNJujY2|a^f!62Ne=wuL9pL||95zGaTz=7|;BQ9Nt zfk$*_@pLf!0V7acf=Bj+Bk<}J^nWfduyx{AzVQyeuL`zf0Mlt%PT{NQ>Ex?(maFLrOrAMfDT9`#8VXSqUqsGs0#0OPO+=H1wOH|%$}*Yi%`ZeGL^lN`A^80-pH zqJ1>o#V_%{YZQ|EuF$i@1zUsl#Q?b2E1dnm#e zVl^Q7-ByOwoniHnzYv1m-Lq6wa*5-c;g2gXG>!H((D|HCjbp2oybD$)AgN(dQ0 z_N6A%a88=90i?i~a-td|;f4M@SI!M~#_y4#q~Z_R$fiBN;D z%v1a`IL(}1e)9$_#3qn)3-B7o@(KVi#~N~m^%?M+spkMsDFiE>8CkRi3$U{sk1zE= zZBc^vupQQ9LgSziAsNgZ&N3J`UDG&APUC4%m2w(?jhL9m|3rkcC5j&)R_r+PFpskY z7-D>{yuTi4nq#GZ&2js|ulhd)`lYOz^?CZF`g|;>(561)=Sq0R#tc?&y%V|Er99a! z*BQ+h3|HTYid>puJ@EvFXCQQ!x!4_iF~yn&R!7BG_vI|W4icHsiTH`n^)rMwpI_s_ z9IxT-3KktWX^j!%q~^KezL?}Wum!Evw{nuBhM3_8zmdJ=D6>mqf`zt`K2w??Vh%lr zN}T%PFmj@Q!;jpD;Y>RCO{#w!7O_@fC}2nVy+hao5F{=VH~vP-SS@m(6LFrgF~8LF zRl_?R)YT|01WXb>8?E4@cS68uF>-&xugc94@>QJS?I@Olg|9U5m1DdQ578=)uapHH z#X`U&wrkNcx6Bv^*%GpI&>;G`T&z`i8y|<^!F6+3zMS4y1F!q@o*3!kJ>?ui@Y$wz zTxA7_8W1wXPuE-jH2_7Z?EXf<1n2T(hHU$OtaCoo?KK~5V?E9he7tcp;;ztPnBq!Q zyoSj4LMN?4o)_;5uxVFls3@a8@Tf9_o3JL}dYLOM+<=j)e6aZ(?A}PuNw@IAlX%57 zd?_lIn$^M}z{RI5a(WNYlC<9Ek|a?0ETZU+*fob=pqqNWd(wz}B~-7lsO24sWy%&31%;_~VW(O=Yki9J~%#G9}i z0^4{&xEwru`v9AHB(sfOhXyX^CE+9#jkYsKiJ#XzTtZwt6|qdx5=}*OB;6?v0pN$| zXXl(m3yPiULMzmWZ1hv0>DEW+5xaxJJ+aT44;FDoVAreq_KqNO!n$-RlfSu%GAX=6 zJWZ^Xxeuw_CYg(Y=k3GLG@09?a(^vzA$cPAWSP4_flhbueuWn7w2l2LxlK zN1AdZeBYyhCy6z-2@BXPTpL$HCVBcg^N*9Xu7*d8^R_{>haHqT6Vq8~L`*y^uoE^N z)+LW`wV>|FUvg01Le|m9vX}N}m~|Ml#5nV{IUAF%_D8maYY7;avD({vAu?&;h`sG! zfTc~wJEHf-8I8RRG2cF%? z;Vq$EuF&-?WZ-{&D23;Ghc`Rwb-dX*lIJR3yv}V7^&00OqXe6t4p`ys?oxcVu$q2u zoXj5(zV2V`(LK)w@R{y)bS?RD?F;@SVd2w}HT?$4qHtsphDx2Q<^CIrNjQ6#O-)zd z43gsskD0V5L~CEULIz0`o7%|P@M~`Abc=i(Pk|4*QGo4L2RMKWHloHG{@Gr$WRD)X z6pLQT0erd$uR{f1_Sy6a9~n#|{s$AN7N_*y>k}#U!B}wnz^kmzR!MJZ_Q$38elGS6 zxCBG*B+L=?OUK6H@2D!gb!0Bsbv{^Him&aiM-+^LKqOe}k5OiWJ^rhNBEZ(}g#O2K zm6Qg$p2$I;O&2_R;#GFrkIorRa}Qodt39X?0MGfuBo_ZwKLVGCAtWi)*fPsoZb&xPAd~}r5&sT z%K@i*lI?MZS${;XRUk;G%;Gat9=HenyRgh-H@3-Pg;AjMU8QQQb6Ar5UxZy-IWf*+ z{)_XdZs+;f8(x($eDTHh7ymrExe%YW`piEA$H|?Cbs>@GrT!yz&qc~#tkVhci8T{M zL%r|7V9*QPZR^DG5Vx}Y@9V+K)3v}Co!jGlzXUg+mT1CHY%Mf7^i{Tp_$zpmeBvvr z@CwKLjb41S)GW>EJSmYLysQUaEu*`b4r09c4F~a8UVIw15dYDK&+|p#ZLc{S+lATb zlw0x-9%5W{g--_!TfY-+0u1UO#@A}26EQY%eVF@p^rXbJ;NO3A9=eU~Bz%ADET(_l zc_=TAM$!@XJ|;Bu+MLWQp@26tuY<|V*DzvAS~ zZvDlj3hTmUJS|y_xd3hA-MhpR8Oy&^Sk zR<{|hiQ_Blb3ro{CvIEXCszE{dZbCLmJ}5FPr)wCH~LQ(&!F$re=7W@fhM1Epp++7 zpoCv{G~U9(nxok#GM{6QnuWGCYc15Q_}{U`hP^nWb5j@7slwBt!b1i(ytozt4KA0F zVu%(g!$!S7$mB*n9S&V*rwIpr=RX9$l~i{QP*U7^gmuxi>X?gL?qgBW`a6E0IdBFS z^A7=r46%<-CQf|kEsqrLLnSI;^244G>kudGErh(LtNvf|p#49Qvui&+KXKqE4*XAY zz@c#)tZ5~c{_2VD6UQ~Wv-}fJ9N*}^Wa5c)-SxHNcM*RZMO4Ic#BVNsv)yj*!uo)} zaiSvX!bOYf+=aCbRe@Un#EG?y6_-@j)y}P`l8~%yRZKf~al@j8^UrtBtE;U?yK_go z8~xP_WNcn#pbkXL<#E`#4Yl)Y{6C^x0=|l>h5jy_T`7TABqeUrl8C>nBx&hNb+6|> zu~9qctQpfwPA-@^v&1_cEj79aDp1)Bl~f%bQ&nHDEeiNg{v}bWLNg0gp+fIjg|of0 z+=Y5^;WYQu0dLyhMO78G3mdB&@SjjtRW4k($nUNK++Ph|&Yd`MZuP~1YIj{_!~E(7x4))xp?g7P zQ$=I#Wz`sl+J%0%81so$m317X0HO0yS&%%hvaYe3{Mr0aESA1H7Mp{=Rro7=I2PN3 zFc0A>=fDs%k*~RPXd6_ski-*|WSerXww$a{-8tVqIO=c#F6iam2?6 ziRj|}4~+y7pF6wk-$om6UNzH2f&iR|w4xe(U35uxL*;zVjWOfr4XCg5`>PukA~kow zh1K&GH85lDfQ5?|Gqh_hTc00j6qUxDQt7Xs@19&V;J`zZ|I5S2i@(E}ZY4 zS6f$2*%>otjOH#{w6J>2K&{L>alnae9)ctzVvuBXCTEC@R@GEjT|^{edbyRfNmLEh zjhsKA2MA9Wk3A#ZGyRqR+D3nERij(wD4J!e?_Wr`crG9QV9EQJh0dU(NPG5olLQbU z)5Gys+|aP7!M(VKeS<8{C5cI2EE}U z<0iT(t7KoGv3jmsj)i+}^}O1J=;5M;=(>3Nu8*pVeb z8Eiqg3Le1UAbb)hQ?FiwIR=OS>%my86|{9C%)o|td^i@%fvdk9VH<7}gb?y_#{)}a zu?;BqBuwq|kluyxE70-|wizL`cOJH(TNz?QoC6zPev6vhEItJl*gp(2KO#cmZB77bm$};r#oprI;PK4hg{0iai>tnIe=>G!<^ASFe z@8n#;^wwBxGwSVnITqvp!@B&HSgaiVKJT?y>_g=5LYRT{=r>}qcfc>-+p$&0B5KjI)7F)*j7qQqZ@b%lhvDm!`Cx39M z-Es8b{!YHeNI33XXnSD2{+tDh`ort1X_@#NkH57|lJ8nt`qZ?HGhKrgJDasLj+%JV zxXj~Oj`h#O-<->#ZwXKj;ePy;1Kx&lvmds_$8lMiPf*hTHd_Bj+w_b^9@{R1o!^Ww zR#T8x zU!2xdoYw3(3*fWU@=&fIEerKfe@a^Vlr*R21IlvX&4jEDgiJ~NMcwfi#qpN_S@M^T zfxY4Kf@&=Xf2)9R)*Z3fwTNrQ>^JZQlZ(*rx#%|_=(l$efRY6|ioJt6t5IiBypJ=w z)6l(-*Yrw3@gOnYSs1HV?~KK&**^HSob4}7E&xkYl8Png(f86p7!FWCHfW?_4(bhV zh0JrT%lhJTk>qoJ(&K&6Fd5Y|fnyKm^91xK&=KLdEhimIQ;O2Ef~h5GIZ5{p zOv?fUq{tDOGDs^z{kg0UJ;3*(Q}$z0q5kzrC21KEj{EWyjN?*{d$3oj0^*ARA5KUPNoTwD+ zzqH@-)JV$p$u}g4{-aDA^q1)WowD73tN*MIz4trz|8iOX-|c@5=z9QoGH!{*?uH&r zDY5(S?Mt>w(pr*|pGrpmA@ktznF$;{b5QanNxgCgbJ&fxGBAIx!J0!)drBJl($bAD z)GgH8%W#Po7i7f4xxXE-6@c+WH(K&hNoh(6as0kQ-dgDUOVAG~0~q1&$w1PBQi|fE zUot3p6J{wTD-N5+@gr*d?-1IDSTmqn#Y5P6fb9efx2@u^dcbx8_OgO;j&QwMdw(qU zXVUt^x`=|guUCG766(;cZ1d7s3;}qRpD02aWvB)j?`&2w)PV)(-<(6MSbs|__FKx( zJ+l7w)CG~`;@;;FW@RGBpid}6dw|FPmsl(fYf#D}iAT*L;Q5{oJ~OQ)Ir*ToR~ec* zDEU50*Y`EClA-e;r`xbzolcr3p)DXwWDLj33Gi2ckHrp0oX>dt9Rry5IP4Szl26bT zO4mS+rLJkVRSi@yv>tKILcJQ)gS3i=E}|O1<^smg7xl_>%#Gw^hmB0FB$}3w;-o`= zA{KiM!j^I?IwSOd;gEhsHzZ%5f-6tU`vv3y=jb=v|vnn@&v~iEjgGp5R19u z!5rWi47qTS2R8%9;C|`gLDKSmk<{x`Zb;5SJA<8?R{z|OUt=gwJl%aBb%ahj2YCNY zc{+glqajc0NY^;jN6)WMD(*fX!JA;eB8dJ?(8)dIN%b!uw2wjmaPdG(ISAo`?Dt!m zx;!P4d_AXC8UE&?%ueW72j+ju4wU)fxmJ|c;z+)Ol2!Py}cGVpMz|9N&gdU zx5d#@w&p?*YCed?&{gqJwweH&3s`^<(9vx@^~KlIse^viwVtvMS*Z5_>Rk-om2#2Y zhaXtiVOw~5*RWIB2jZmtsbdTeCtuF6aYD!SWe&R|eHuh?4psm_;gyKFo_m8{^FH^JWe3!TNz_O5}|_|ADV%aV$0p zxKp-3c+$!e#Z<^a2xaEH6pK})qs&7n(_=h(*u`h2?dg{s?%!)Kgx%^!Tib!N2<@I| z_XCv@8|GRa!lGGzg`|zTEtvFcnvdd%-8RDEJRCB4TB@JAYe^h_q+@Vu>cHelsrlLr zUqhrEXi?uQtDkv+Ug`(0Ch3@(;syp8FftgJV^^DBMMmYA6TR#HT9lh+VTO2 z-aBZ-L&LNO(~bim>`J|LnD(rTnL9=NhM~tIcllu`_=m#?e)X_a0H|7y$L)ExbK8-Q ze@VkGN6Dci?G{DDDNR84h2zG4zZs%E>P)?Ei1zydsffQeAob8-?e2k$KR%G~`vwuh z)~-aAAJ^6wjw#y6}PDNh}tJwM@ zHz!@RCRy+#UGn5)$ML5lcBdmX+F$E%q`uqVu`c-q;EbmJ(eZVEZA<@zCcwj=ISxxr zo#&_o^bd~If!c;Hp%L_*=r}r-g3NnUQ*ZC*xV0amkM~P`x1Y9)(KxL!NB?J2)+Ar& z6ts*)7RKpc^x?K_$8n#r6R#wtK9;QQPfC3-8UH6k>NP3acO0-A*{*B>$OayX)ZNLc zowB<>M~e6#a5(O9Y;dIBmj{PvNlAmWvggsXnsHq-;cr#=dllZT!au6;J{A7o(8r%> z=;DAwMK@y$!pBa((IfqlO2cH4k6Q-V#)@a7&3Slsv*Yu$lQNGPFG^ALgfc{@h=NgH)RK6(8=45+7Af(_fTO?vePo zVQTUjE(1-W)9?<0cn+ux8{Ue0uzYN~%M~I;rtrfuAMf>v$1e9zxFrbyp9Kh)aYVXV zIdO0YOQdZ&_o(zhmH&-O+kBVU|L1=5p6?x3j$6X>RamCNIV!AIVY3QbRM@J*)hcXL z;Z_yyRN)>KYR75fNmrp;g*htBS7Dh7=cuq=h0Q8#QDLhJSF5m1gJU1#qqPjhXQehYo)bFYiFEgXPfC*bv$AA;hr;t) zz(t9G6wY|?b~^i0o?AI|Jd?`~&y z9+{rF>#E#Tch}5RwyV3-T{AnANLUh3!3TkWSr-E%C@TJNAqEl&x`=`#(L@jpW}}t)D*NRDZXi>y_V*fo~Jd9g;J;`5k6NPF1pYeUY5mW7FA9$Cf|hyiaj9WDPpjvH@2BSA}|_!p`g-8H2iHt;j|X}}i^+=1e~ z9QY^i)POw(em~$;&%_B0p!hi@1w$gO-G>0b7X1FbXEa_;XVw!L_ru5ki{4Zp{U&?_074SW~ud$MP?O%+KA5XW(>kGKN8iYsVeDbu0Q(ThL zJ`4@f)h`WQon$Ct(SWDT`vZiJc86Zjh!AU>PBZ?HwXmx1w{&Jb4LH+-;TK-_#j}4J z{O(bW$ZK7={1_A@)59Yg&hc5>eg*T_koBtR zC&VD965xbyJ)-Z$zMjwE$JGq@lNsovfMzr=2lr@P>&rOmqyIQ8@FL5<0K zEO2?sz#lgANb59|j%3WsZ4hl~_20>G$W^09cpV${ECbGTvd-07LT^iOAk*r33~<6< zI2Ff#5{uGl`0q3HaQ6|7kCEbZ72u>tl5+SahVQj*HuAxsTl)a#c{Jl7e7(u_3)Xi2 z^$hsW84ml$^hegxU&_G$2jD{yJ11-b1~<|3DMQaE&4V)F)X$gaHGuX;Q2IzNeSF3< z;C+TeZkT@l26a$+K9^q4D;e;AXTU#xZF)V+fK&gI_Q_WaJZYbN4oVG845UrK)98Wx zw>0=G8SwGz34h2sW1A*+>3oUd1I=2`XTV=K_2ll+WoYf2()F;$r z;5=bV} zt%@EkX*<%lB9O2HT<_klEMk<0*V>(4)9txUK!fVS$N}1qUkggBPJgvpE2>H@7{ffE zRM64)m;`_^3nLxu*T)vzmf|hl{rG5I)V9iIFLrFCFJ=pRuzbgB%QRqc3hEF>A#my~ zP@owZTNx?@jgBeRbOXn0jjL+YZ3kYk86PeXYdDm+o~sQjdrZxCnyTltS6oGdj7`)0 zpjZIG>(dAPu*py5(L&GjT}&^PP~A?;Yi#Q3%G-TZLC^7UF!XS}P&r(;`H$vll(~hD z4yd)Z2c9A>!awd#K~2)xg1Jr;V5e$e^xmq?Fk4Z5CgE+mj@Q#@B}Ju_hfVShjw(>C zx>-W6SLT=0{8B+J&Mes~@AZ35$d~VoD^J128`miHlGvhC2X4<$vTf78`(n^J?za1j zGoahDQjLub+qR1ku3m#g3#hQ#AgS9}b$UWbjS48DfysoV7}e)ds* z=#=iH1tF}N+KAHPi`uSD64Pw+8JelNEgX!o`$3%3Mk1Vs>$%!g7N70h@ zQaO#dOmiEC3Ei7juHS7r4YztnZB$k9HnnjQmKD0=UJY=~Br_Os4si{}vJ5TbuJj;R zS*1Dcpjzk0(_QdXHY>d|?*E5z4~afh_#@11YPr|(6`fY8EX*_v*1^N``zH@8)nBWt zs#3@PXRHXlSPKqAA9)?JFD%$s{a|f*Ip45Ixv${ZiVL>JIky(h9zj#9W=E~GI&~0P z6SBLnoV5*{e**2gf!icWorZz;YkSJ+^_)!web?KxmV2;&RCCSuH&G;Vr!AK#DxbKa zBXUX|Se%@#fJ>*9!rj5SyHw?n0UnxOwAA#c=O$;XQXWD8$(f zGn!2|{3xApP+h9hj#5r#oDbNNU0v}PXMFvhV;~9Uiz=t!8y+lK!+7zoN7ti#sG zrNcVs@>COJL!u@=Hr099k~jvc=$t07LGd8LV71pdfzfO#KE|9V15?ydb*QMeYB)h- zHNvNm^z@L9d6J*6+k&hwf`NV4Z}{Cf2;Lhv3Q1xbZMp50U{$$vP!(!9-dmFTZMgTkxY}-2$!jJ8*RWu8X@NxTOREqrU?iw8D zx`R?MsH%5>MkruaS!dIo3QP4_(H-4@cw0M~b}e)&+7cj(4TI70>g4A+7!V3_gaa~6 zR#VuiGG3WJ(hzxB>93t0WJ2j$P=rAdVRAMP+wKXaxi7}=`Qo^K!*@JJ@(PPKXhwh5 z!Ng`b>QeFj1$Gv-TWumST@rga3BIL(s9(Fj^A08(u>5uwQclCTodpP$)>y z5UhUKKJze2eMI+SG8Hkrb~B_p(!xeOUx?6^S_j;=a+cdx&UV}QQM%iP>UQL| zK|Y3&jr3rGT>_!CT`YF#l@#dNn3T!eV>FftO}ZmWcsmG&6a{tOm`RD4y|REIOtINP zISDl|3@6TzWq~4lW~mc)s)Yz6`H&cW;rty)io(xf`m>Y1?-pWEaS>ryw92Pf>m<~X}X+e!a$1_GL zMDpi}Od`gJFR;;K5d=8QHT>aYUvX3RCQ?<%kr}50i%PK zJeFt?-%@wAPr%kui}-4qkI|Z%!YYB;EwYnHkp2Q+Wig>eBwD(YD*ZK@NOAyY8gbpE zYZalB*o^|2f?(E)8_-&BT8LP$-bm=7>s#o zLQ96W&&h%pbL)nd>Twbth)iFKzON={wc>Z$CUnCFI+*_L=jZES6|rtQ;~raD!h63Z zKQnEeR?|*g>kJUCmG5u**ad_<=;?e_u4t*g*R}Haw4j@Zr;(@CHiR8FBcS@4*J|G8 zH4O-hP`A;RH%6y*2P@y)Y@-RC2R;1+pQ7yJ+lH|lg=amt0)8(>2o2}`b3FZSv>kf-x8+a_ycIx-yPs*>F@{(h_Wh|L(;~|W;`A5sk`8UaPA*Q}amZ$Bq z`2Sxz(!QK`m3+dKe~-zN{dWMTt)Wt0&cjOHeYY-1eWY=g^4Mn1$-^(bvXqzewUWzu zT8%w8{`cYmomG|caz0gZp%Cf6;7R@f%G23bxtH^=lIN(?NYsDor}Up-l)j2T8dE91 zWj5vf5<=V||` zM0q*4Df#crK7Cyq?M;uTpC-!7c^Apeah0%8a{PW_%7@+DGN>kBGW2ht;rz+{uW&)* zC*|dQo#gZl$!JQp{}LWX%NJ-ukR;!d0|Xj8(Ec9*kCuPoag8YXUyM95#hKRSn({aB zha+Xo8+0${5)b{D?gqzO=wI@8p>Z4y3(Lzn$fKsb;BjU6k$cH6LwV}IbW_gf-fha$ zdDv*mMQ?Du7te`zq`aJC9D7FQvSvSoNy^cbD>@R zME@Q-tMdsW4kR4&ux`Ph^k3u`9V3#y<1$QN`nA6N;Y}fkFQi?8?!iS``SNQTV?0qH Haclh-pjW&^ literal 66352 zcmeEv3w%_?_5a;$0^yY#6fjlPMS~_1aRWiJAexXY+?5TaJe2y{giQjeA&JQ@#0MJP zEONcB#tJRs-!n6J_h#8u+u!f^`ThT& zzn4#TX3orN4u=$pjNY$B1VNEhC=J2yD9I-E zLpqhgczzKNkjtN4DSg9q0k;qo|F3 z@YvXIH2nA~o;E^rJ=R`_C?6LVp2*=wXs$=RQJ&`c%8Px&*BCL9v|EHmJz^KtD}0uh zFMO$Qm?`*aga$u}M*1rh{EQE698I*_@%845dhubYsAq)K20e2=_Er5S?Ujpqoey$6 z@!^*=PuD0Iaa&}AM zxo4kSFt)j2>^MdO(M4@g_31O`Nf?$+f(bUVu^1-Ol)vrZp<&CKS6_Af3GL_1_PjOV z;GQw>7&xd+Dnk#|7egFPPe6>yu>N=4Uy&)zk_a{te-8Y0SHH6O&!1JzZF;ufq_VD; zx_>jWaeY(JeUkju!5zp>_&fw;$0f+o(Rd>Gc}dDY3&IkW|2zqvd(i1b<)27`pSY5! z{3T#iBDg;ZJ()?$=O%%FmV}-^B%!A(3H*~Jc>b0I?o9&!G70>xB=E&a`ZYNT{I5yy z{4L3Ntw_S>xlo8ibaE*>Z*BO;+#un&Y0ty=<#@4TJrPr$1SLA zuJrZz-)U+7!pscvd&Xo?p9cN=tg$~=|L&9w{bowH}m zDL`+jQ3t2CwgHqKOR95%x30Rf$%&kC9#=y%{rM_=;Kn6$F9NVY)UH8qt1A~LM8VrB zL<=62t}Y$Nx>r?KzGN|>nfq^{$sf;Ktf{T5Uf{1u*dSnn-7)PIZ|F&-jGOamV#);4<@8o>rG zX8AzL#cV-km8Y@}Qiu!)bERhi6rtYZt@L>p0T~S$0$@DXT*F)0>?1gciw<%LALJj% zo&rV<1e^NK#B3JGTij3uIrA)RY4J2xH#IlZSJu_~uJ$akqb)XgKR^^XSwCcm&TX#t zK>(cP-a4vemK)Gi#s$Yyi=pR&m4L5?OrUO|2WG@qSz8AkE^n$`TJCg`D4eAEtICaT~h%-M#0$pxMaS$sKb=#Q)^tGViU}HJnk7cwjdhIk449g z6@^g%&0{7{!MZIKfAlX6>ogwgkGK`7G!~|_U&^;i1MoLc8pPs*Md=|@e-=waNHIyu zKwbJrb?D)BIc^IpLF+<`)Cyn6@SDodxOx!P%odJ^MM_5rp5KnJWyhb8KSatyKGj)t z_*d{`21^c+u4L&!k|NSqv+@I^i$(g?KV1o8`b$+JeHAO;PihcpKP#UqT`$tU++Sd; z!76D;(_;aj?iKV>dRT4k5DC2al_66*pRuoE z>}N=J!YWDS!Y?!6-Dh$5{5W{0*ypNPga2B< zSH!{Z74Y^r_-_S#bsYTn0^Sh^e^|iNyLmqhJ{allzjHX4&Gr&_N|JV&;A0FR!rdl# zz6q|I;Nwj2UK4!034YiFC(SXQOhKmwfLsHJaE<5}X#nka7|%8noc2JB$MCPIJgpgw z$ME+Fey#yTX!!L6FEqg`Uf~H6Gos0O7Mb8soaobNf|KqVPm2kTB}VjVHNmNE<5^*X z)7ThKy9q8tpJlB!!HqGdj1ChV3KMPb?FAUmd=uPe01;N0;G<0NMJBj;ecfn+pKdDOVuELz;H@V3XcK&e34VqN-fn`Q zX@ajd!E;RT4io$=6MT&co@auuHNnp|!PlGMV@>c*6Z{+#e47a_rXo}BkI^4F@FNF) zlwucW~ef`IN7fz^CbomiE@4a9kbi^rb|)mB8loO^m?EgtH!#qyv%BV-U!v zN>qLk6=F@PY6h(KI=} z2f{Z-)8wQb2wxRVlcReeTp3N1gL@$S(`cF;+XLa^Xqp__1L6E=njF~!;Ze~vIj{%9 zL!;>ombOIGGE472YV?;JRrEiaCI=P$kEY2nMgOB|a!AqtXqp^R^go&=2NeB}rpfU{ z|D$PgIMM%TnjB5^Kbj^76a9~-$+1NLqiJ#|(f??g97*&)nkEMl{g0-}aXb*VMAPIj z9tiJ0V)Wm}((gyp6=FANn6n zlcR_JN7J-mME|2{a`@2yXqpzX=zla#jvx9TO_Rfi{u^mX`xB3nw3kXu-jSa0NZ<6? zap}=<>67Eq!{gFJ;?ikx=_3#KZSP-k>CfWQAIGKNiA%p8mwq`ey(KRFTwMBzxbz?6 z(htU^?~O~Zic5#$(!sd&vbeNAF19 z9G4y*mmU(APK!$)`9s|J$E81uOMe`fekU&ddR+QtBdz}pQm;>gsbe#Nx<$VRaYfyy z{{q0s67Wj|d>ob6 zuFJM7!HB<1(Mq#(C~3<-sDy@XVa+r!5&%=WO0(JS3`N+oN|}6JcDgT3f0PwDFI%?) zEs^~;k*l4m-$@zjdp-B_Hbn7d47yK$f@~Y*Wa>X>71EA>5cRbo!zfVOvT4&t(Ta3M zy)~7^yV|nTX`aKw$W%gUEx!|GG2iLlZ>ha~`lUdpFF`^ldmDZqwnfpN&F)4$w__hD z{+bGg+OpdLajE}Q)Y9xM!kFb&KXiwD+2y*9t`a0&f0xCc&0b5bq6;~Glscq$5g2X# z=^NHZeGhu2{}ybk-Y9!iC%=pLGglk#55^{Db zUCuR}0A~ja9bI5-7Vyw8m9th+lCe7lP(^#Lks4%x{e(z;PtO&^z0cD<%k_yYwom^% zLj7UXGq~|C;Q%)dvKIE}?^dJpNPmK~ZlTiGiPA20v%Z!}Y5vBt;6XX~9Oy%D(4%D) zrrr#urT{`uT38RdoQ)K^97oWTnLJnF1Q+oXDJ=5F@l+O1W%CpX67oh+O5OK-Cp1QP zAVG$p*hJcJA`P&zuc-OwR-;AzeTsJlDNYZf9Teixe-9Kc?fP_AXj+y_J4In^{xiyh z%`Wv_{r8B5httS0PLV$wnsPo=S-+0aHDw5?HJn-{H2gSiLL0Rfw`R^1e<*-I9-=eeTd7N!Pzn9&xLSD_$rfR9((RWK6n(t@xFs)(b>$$-K%# zgH#>?$rgh3JlMvAT?q8o4-?;3bs(;&jAbv-wLv8`auuX0q69uXtXMYbk5REuJIhk7 zHHuu{iLOUlSgmeUu953HUm!}zN~8l7HKK%qS%4v>Q%Xy_{c1|x+es-kXrsLKR7raA zuE_x85FpU$MYJ)RM?S8it|Hn|bvI8D?JjLDYiTu#fpl09JL@<0_ok+S~pU5Xu@6t0LtnCa%;;97434n5-QCuBALvjNs+OGA~wzx%%&9K z(Tiwyro2W~B6R+zFK5hawikpjnI-*6~UJ;kxK9uV0r zpV}(n*(5@g|21WXCQyAP_o$-wDjPn(K-qBEs#vxvJC6E>0fCb;fgnAyyN1za)F`&Brh_TXZM#g?SOy#>s4pqF$MUKSfdJ*c7#- z5MdEQyF9cclkD-Omv1uI--KbQVfMR^{e^Edz0j>S*qNZY99!hJ?I6n?nsWcIDHvVX z2s0M7;Vx}4375R?a(k(~&Y!QJbSc>3otHy>0;FubysooUbLJTmVr?LkH26)@?&6E) zl*{X!37&+(4` zeT?gH(8u!gJ6(Y->H5RSb35v?)8*hSW~w)5nFN=(!Tax0kBBJ<>P{?JXonIHM*HX> zv>pjsN0W-%C{(&qS(;Rx={_?Hl;d{n_D>5tF+bF_E8gzb>yEceemU4Fuj~XfTCcMr zc>;|tsGR_I2x@f+l)5lTZU+pf+?EOiE^TDCOIuYA%~!lut>C8MLEmry6aWGs#G-gp zZ&EC$?JUC1JGP)Z_x_GD0eDyk<->Gw>6ReqQpRyaIz8u z!&fk!hN!%!7ow!2B+qv|=kW?K1;f-%!<55@sqJS(AxdWOl3Xy5ogKaaIgEphec_WC zpE0~HN3alhqMF99uM|9K=*tc9pXerK_^itso!RvslISBjE)8OpiQw&u>x&hLb$ zVMBJ7fk+>VY-&#m2Y4IT7+Fx-p~!S;A?gHFRa-^FN84Z=nerQ4q627XtlykW>>h zZest{WFK$*bQfxoZBR51tSgq0@K*;5fA!YvZOF~vPK&O#N7D#zgVJ*j`MFz*#z6<& zwDi2HT$y~;e7Wriwp|sqpAy&#NARk0uK6GO9Qu5a3%j9iP-=HBtf{Hl@YShsR!+-( zF*NKKmYuoXfx{^-@cjBmT3g0R{y&I{{w|uOv)oz>Xe$D3uvsogm)v$b2qAYfhv;x= z{aahcGmC}={jF|>Pn8#u~Ba8Mj@uhLF=h@@FfEk8`ec7OmPZ)Hp*qrG?VY&kfP znTX5an+D(ZWx}c`+DUrarx=ys+x}jX3Cw4-?IU)1@(=1a_aK+Sz5K#ZPE`40IUg+fW?b3RxQC!ZbY8|0HFRuTY5ynH^%WPI|IG#GMQ1Jo@l zqC87TX=5KL-DsB5orC&H=|-f#OG;-`Bi|{dTz`a)eYbp8hrdfc_vqg%pV@?fZIS&j z`TUYl#^m#3B#)8LHfFw~%N#kVQkQSsybDZ@_ZO5KyH?N`sRtNO^_4I{;pLcq3_mr{ z)fmlON|~FmYN=^w>%D#YXdJPH|I9XJu>RYp52y5WHhVprO^Edp#)Fky-L$E&3menP zx93KRA?TuaSio{42&V9Hh|8wTqu?3jf20+$;rJoNo%FtFjHY=Z@RuurEG>4%uX zh$a=F)^9`)$X%!Pq7}n$#AU?WjXfpq&(oHKON~Ugm2UiW8?c&ombf{CGZBJikaIEd z(F~cTs9lN*2N=fOMy90#wU~`rL=l72216+909>DVAQCCl8VbwEF961JniSa7$FSr; zj2IR>LKZ2c2=Esf^PWNgYO$OmWsXmM6AgQqn$4#XMO)oTg~qI2PXSuUQZ{^J)&DUN zHUg^#HLJ|=vH$Nb?Npc6kWQN~S;fz>mNDwgTwsA@>$!sCRn&oOrh!z^L@M%qMT$14 zRMm?ETP$Rvv((sZ70_YwH~P0K+IgVp6P?}wWGGDNH()+syhP({YTE=-qjs;A=r+yE z=!}h;8ZccVjDI# zzdra8WZjrwbI1^x&r!~#T!PVvvazO!9q8E3J)NUei6Rxz`IWj&^Xm!&^@$DuW3D#6cuC&h};h++#tpG%YkKl3A1 z0vB&Gw#);YqCSiM`UgblwcR)o)6qewO37{(VpnZ2-`EHb1&VgD$pIm6qkOi%tUQHI z(<7Ta`M{@el^3SFwf=5(w>uZxf!F|YY?Is4AeC6YDzNP85tsTeckV{)1j%h50GsQ1 zm??U0P(pB09KG`LI|0V>P*JhV>W1ym9|ozkB%-+zy0yt=*$StoEca7)=(^(pNIiZ= zDD_NcW`a9!IHxT5(G3gAAiEb3d$Bj?&y+``X3ImJ(2YJ@6-Q=aTZn7`B9UVq> zH&ibDhEv>Xm!5&Pd!A(TaPXl2LTCQL{I`2@;Tm9Uv!st@fC*CI_5kt$qB@z<2z**_hKd zx?8i-($THzkOpi(Qobv9gDdcrWy#OjKAisd-6VzcARbQ0XbHU7OjH3KvFTZ8PFi$! z9$I2&%7mGD19stxxPV4CPTirUDUgSAVOr&z9|G%@;Li1+Mp9(wMl8)zQe2Lg<(uCI zU*B(5DDMon+Keq|>=$x^A%Wc>bR!7Gxep|ewh&nsVnyMDG5^M$dw_P= zlpTA~a<^OEOYJ!hE|J}i&wck&%fA4XJ$F*_HdhEUxsv;)+j2<17U1yJT)dvV488fs zyO`S_#1E5iCQo!0WEyKFaMU8VvD4D^s7R0OQeRUXTjiT~fg$ct-oJ=3<-PaD_S%5?MpJLoPtd>j}tphp*fj7Cy4n_LuVl+{b^!A{soGB^yhxkBf?M!8T_gpeZ?R%c|o)f1F}L-G~QPzP^zsokjR-@^Ui$!^ErVd$>~ z0oaj+T%8^p`k20tjwn;#54+Jx{q}bZ%i5*ii8!tLF%UU=KlD>Idlk%1O@wp?oh$& zoIjnuixmyF>J2w~-!l^QDcS%fxZPJofc%|qwUeqj-teDO=Gg52KnWE?6E4dJ{_!K( zW{4bokvJXLoM}u(*aa`ewow+q`f_vznuFzFbGj0`7V{*vixJpDQuh?e|5j%v(oD~C z$XMzdsgC*vHt0su(ExVOx{uIU@5V44YKFrjh}QAD)E|y!Y|-Ck1mgY!LX$k3&+8ZAo`*Z$vfyx#)6_FdEFS`wJrUvvR*nv9D>Wg)0_T* zG(E>lHU;VC6=iTzx0C@-dfDVUI*ZwY+OE(tm{GLiQkTIVf-(hLv>-XlZQ1XGd4!XA zK1d=;a$JF7aHZve7Y{siOviwvtPNp755a z`@HMK1lIlipg6w!rC4jah;A3Bo90D@(M^~@H+8`7R(stR-8X#qzp-pcWS?h}v_^)DmZ-qiGOJtPZX^N}|a9Z*Wo$p2<2-dyryxvF1(E z7i{-N*DiAKC>089US!M{I8}x`GZOy}gy9V!2j^*6w`3MG4=H~;O+=sTSMTD;?BUN@ z!>uR?UeCorJ$bx)^cLI)4l9O!0M0z&J$ePfZ(?=O&S!GlaFprEX7dznWaMBTz{EO$ z@YD2w%>mGi*@zgj7pro;{tc)r*bNa}CWYSsDp8MIksatHJjG}|#4$-?mjU}idI76R zfQ8S4&Kr^7(xu(y#U4!9P!Q0Wi7mfb(xP(0)FO-!Lf($ z`!?DkVuVB)rVg1HQT@7!5j|?mfmcFvNl(}~^y1!j_)Bz^F}sqO4Kp$2{n_vch5>FRu9@r5qL~i^vi}Wz`*KBgbmC&Q?dZEep zY0FMW0e03%+G^9&&;srdjJTHe)b@3f`-nSwhF;Yg;zk zd!gMfm@&O;XCy-Bn#+d}RZy^}@j@$=u4kmRWp{$ytvq1-A-%5v3`8-7;8z39*8*uz zt(?tAF}}F92U2^{6RcU~wuyrwq^;Lsdqi$~515MO=jUdZxI+){LnK_|!XDFO)V>C- znXMlz&9tS-!B5!`@b+2@Pxsx26TA<~NeTAoc60+S+^ql&6`+$DNN)2(*l41mgRV|m z9%39?(JDO(EvaE%X$P>J?FH&1zM^*N0wxr`Maey^OnCt%mtLhzX+qeBhJfR`gI1+jq8+SlbWM@mz6j1m)K~OT%EkEBK z?uD9SKcmZr1}tbmF9%YZWY$7<O zU@pPX#mlP@LE;jjK`%G?o6Ne6N^-;Ff#^;}Bs17q@_fwzNS&LUd=*uuc@fk?L zd^z7ni;Wg)s?qKE&^IP#4`@5Vg@MkbJB#D=BOuQe*leRi6l|2BJQKbe=4RnOC$hso zb&*9U{BbrRe87zPZdY?9n&CZ(^!{2ewBAY%#70!hv*YOKoId2-nu40t=l^ zyCyHq@vn7-Zea7%W;#FwVruD6Opi^sqOq)f;O{ivml17sV34E7m&^N)>5P_GV87h9 z59sx4sAOP^4ZD}PpTkPSyTa;fpYEZoP@00PXUyy*Hh*c2ln-jj3hIMip@uP;>Gy+c zsC|VFOdoHh6kyiV9y$006v8x)hE`2-6SXZBdH|@Q%)#+A$1*Dunh==DGI#4W zB69@GH0%)BE+r(+x3N24_zZL#ci0Xa2NGn}Isl>v+gE8yK({D?!>RJk%K!=IfL=o# zAuZU(*T(g61?eLoBd z-iIb!HUqH@AEmi1d-R)L;?~TGM!Ds%e1I8(A#_iEfOSL;(mn`bFJ#jju3P92Lz;VT zGyF?~uOD2ZW7pLA>>MZ5Sfr06R2WXh4XQLOk zE2;WC2uQd9o6(AT57S~L@C}^zuW4ood;=elK6XlUWYLUDEn(fU0v-%v*fXSBv~vb+ zuK;7Wre?9i3MoM^;QAJJWx@O!#p56YW}^^hq6iB&fnMRaSEe0?@hL<$)*VZ+T-ul* zJ3TxdTxa(3X;@sk7E{V;EF`B{A!i=O5+v)t0u!U=61+5QCAr++yvRLG>@dSnHUbkQ zJZ;IW;%C!9xDq<~umWc-$}igBQs2ccaGGMl{x~X=($UukV>0UsY&Od*uJ0|~ri8e4 zWKzPZ+JVZ3l#pBK!!*gIr0DykL?AN+g>~}4b}lJJ#-)m~P(#$flOnXEKTKqpjmE9Q z5B;t%O{r{uQ60fqzqXUQO%kVQYu8YG^4hfse9K6wig=-maGiu@qN_B$`L1Qt**^VV zni|Nb_!g4GVdM~J>7`5n;CW#M&lCaJSxb}GZUc5Xcr7Vr2pXb<*3;^lR||atxvUpi zMab%iW;IdPbxfVPgRy)X+77i8=`Gv%sAP}@rv{-js0QWaD&*E0F;hOu#29)6g@Fgr zODk@85Os`j$PZs}-wYgl#a)FM+y_JcW5VxN|7sR~wr3#vDWt!PU4<}9{}UiFCjGxQ z2sKN;F^tC05u0<{&Hjko_B?u}*Agz_X6!afGq>c7Ly&Daiqlad{1YUIEb_%JaSB$I zb#YcrG$;V85S7B+@%o<&$WjDg7yA<%9D(aKa&|DoT7Ca5nY zel+({`S9OhO_{z5!sX!U7|HPY_+f9mL_h?cMF?XPUJY`Lgh3X_Aw7?3`Jd6tJ_L~r z3u@@<1RSFb&_X*FkZnN--H+5CA`&t9!E@u9Wp6DBE|72*!N6hlNjBvR9F~RW6PE-} zhm!Rn@%w5E@zh^L86_y zF-bf`EwSFcj@r=-u`XdXfn~c<3O6C|B`jWG!3KpfKJ3L~mo^O79)!&!i9*F~rixWm z@vOeh=NS3=MQGlPaSHJ{G^IZZa3)P4`UK;DF;(!V6*$58p_D<4hf$Wo{e?e7Vqa&J zyeO_DnfmZMCZ10>O6J9t>_;UZHw#Ot@g&wo7jGdabD|5SG04;cc;sDygY4W3IE-9y8b*m zBRpFF$1W`|n@;aXUJBoxPHa0&xm`WGnSDrpe(O?SSDuEwpvM}!X^*Qa+CORi{RARZ#YGxxwpbh@59d0#GmYb>GHo%Y6t)$Do!ot5C-+;RCtujcec=a?S$Zb!sLc?%Trk6Gpi$LW-_y^94GwX4_~(T2~yK ze3(U%5o$yMltXv+`(OS-ZcsAip%-TMyd3jqaKbJJ>j=Ae{UCfMIvdM}pA81Fj$(?T zv7N@QS?x0J(Zsg{KS7WdBdHf8>YOy)|FV+%j?3~X%)AeWn1}R-H;^i)X4kmn`hW6! zB35wPrB2VJ+h@h{(Eh}c9MgK~4H}q0+@*U%J{!vWa6}$DyO%e;MGnqH-ObAs$BVQvFH&s4?$safq!}GDffXr+0Yexb z4>WEKm+&`m^QD}R+4@?PqyAt_x^V@fTiNhI8oTTf?tm57Kc(!@l$}#hG!t>5>H0@6 z03J9mTcQ(1ye{oSo<0k#BZok7fL33x?g6kTEOcAHiWrMkv5GL-U#73v-#qkm|5~{# zdZA6cGo&rSY5oQJp67|iD{*cKyMV)Lah?k`@!g@Jfm4<@aLUp%3hR0B z&F{iZVah9}JaQJc(Lpy3b?t7)`~G)a+QsS0BB-778ulNxO0bg=pdbxBC6#6sgMEe9PQ>ZfTJ5@KA{72y2I$rWZeTYI%6k!qf>h| z`wco{$90OHKj`T>MxFLXP?{txI~-b|*GZ@SgNn7wG~gL0n4iK4mgTC~e%J-0SE z8+!Vf%W)K}`;y23>prDyj1<;T`8yNnD?8YFAM(b}*xc$Xx_X3Hc^a%ZX1@!QR0$Sm zhhX+GOyTz+O0mws&T#%mjTe8(j@|8HvbqE_^fL3sT*wrhs1a}!$}~SWXs$yC*Y zyf;Z2n+(RC*e>{0VdB?8m*Y+UESKXY+)JTXh{=TQA}+zv#L%HV{UYE8Z*U*JB!{kw zk{k~f_f}q_fdPm5Fh^o?qrZZBco!H02bUq#5)&GnAhbX#b}4kMN=uWrTL_H`j|r!$ zOI`T2_$Ra7Y`jsg){7%dx4Iv*GaanD)uV8rU0u`I%2yvwUT~l@N4!>6ghl#izOJ5A z+7nWl#58`osde1L(7ZDwra?M0cQGY}h zSDG%p7;&1=-$JPW6@?6K(y0P0j)WH2_+1pcNR+NWy*?5-AZHGF+QHAt4#+>#Y@{XP zjioATgh6Hy=ZO0%bEC+hPD=9#S1bE z_G=lz?bna6YO4X7tlfj(W$9`Lrsz^?F`vqNAy)xbMH{?LD^3k|UO(I#U=;$aLVvY5 zmHB}IT)1|;DF=^_&MbutWj~-{#X&r0@Zh4#^)$PXy%nD+a;}d^okK3@X zqAS`dF7FsuDDUA?%`X+_zEX@!2iKocs`@3DcaT#XsX8%D6SD}llB+SC0h}2)zVtt< zXpK0wsb~Rex$PThFvh`67zY94ExZM58M;oaS~gNGBc#RJU=@3nQJj`OI6K3Sb37zJ zT0cjB`Myr{k=tWMySb3aIJ8R{b2FpFdUFQ=o7(yOhAB*OYtzf!^k&y1)MxEiG;D6| zcFv3Ln28~08TYu|-k+3orQU@?7_3>hrrole(iZC4$fQ!b-;2(3w zaY;A?2WCj zs5zJ@|7rq3KG3Hau~B;%=f~k9GA3BognP_FyKBR@*5XiIHfG-Ka@&j4r!K}Z#H6m9 z*+w)65pDXA;!?uDoxD&#Xjx9Gl6P0iNkpL$D^l~me zr@FnL(c9%WzXp3UGgRIaoba9#i@Se%%?U#PDiR|5TlE$?+XN(8NwYOyk)H4fV$+o zlsS(2aoD~O&a8eV$46}H89?_@0u(js;SvpAIiDV__qqRFr7KW~67;~VPzSmKu^|k! zh`g>qYzPC{}IZ|fs)yG<31PsBSk&L?oXgu#XCZw zt4t3MS7d>nS`Ljb~S=4`=O>L|*i_ts%bSG6oV=w zzy1?2(t+9wMKmxtI9p32gvYqWK$1WQYn>vbeNam87GWSdBZuW7QJ80x^fZKsQzHWx+kpov!d@%;A=T2g{4KE7NraPT4gc{kk1clzw zAp$6*hLylxO#FXk#L$wr(V&!_5sK3tI^{XcD&ejQg;+Z?aqDyY0bO5#OnMM)XA$~< z2|wDSB*i-zoa3mVxPp7qY5|rj?(8CV*@NxWyn-BN_n46cLprG_mb~z9bUW@m8DfGR zKex7K4RYODM+X9Wc`2_4U;TJbKb(cHl$7N0Y6tbNaAifyBA<%gC%~MEvc3ZPGy=U% zuc()0D?a!@J{(3*_R+nAe^R6BDJ~S{JM_pR{4deabW$c>M%#^0ZrepEY?w0U(p*A( zMVF{I!HG0_c!6#k3h94YONo{2=-@kV{6j`MQ6YBg9{@rh{u26TbSj(f;b?zlgV`lP zHksJ$rZ9xl8b`Me{m1q*=Ocd|m~zA45)ueVIo%>Vg^mIDG6+AOrxUX6I3W+e&f2;s zyA^e4jeml%|HI!8{`gP8V!XeE#RiUV^AFOS;Mj-~AA?(fB5vH6n9pt>kPH}NViq5| zSm6zSg;w}{r%yg1s?iG5=)!o7KF$eW{4_CXcr#%#$Zm6c(TW(fHArHLqh$Cec$5Ba z>Vx1F-cO@J+)W^26vj#+ZY?5tq=^|a$1>3+MSpAr)kKUePOyT8(|ZCMCbf!*x$2?>7OB4oQI?s(8@wmVk|%mVcU{I z+R+NyK@~dwSE18$QIe0k+=kEJq366Kova|Cpe>~RJ7emD195%FaNfB>bk40k$xM!R zGu4q-mS&$odsmVpu0s84T(hJ>D3aH`U8>?eIdy)jTYHFfUtTvoU(xRCKoqrZu-B+d?YQnU zf(`rCR!PGAY9%DNu}K6gdR`3K#r8p&^1501@~Vx4lvH_DCkf1oi|s3>=aW=!LEgBw z?Y;}-bxX$=wH@>q6c@tpz7otRL=$qb60vp{oM5*DM_+Q=P?9;&Sr~p3$|J@}-H%#6 zhubSF+7mRzxV0cnB^PQ1ufSu}o}dZ3ZKvG!D#9|$w!l_wkgyUe%c7>>KYA~~q(;?& zg{s3@`daZ`ld7#^^|2rDI6*B(0~_&P2`i%VEPQNbKE#gC3Br)>!Oa(X-%$=uA&C^w z9dsY&yG)AQc0IZ*j)gnZsq4m<26kfvI2(drq4P19)sSli??X}{ybnp+0bo-(z3i2y z-~9+BV}@n~w*$1bgzpe6quh8q6E!iBhdHXoWY&d!=MasY%Nh|kkkITzB8yFJXqlPt z&>}3W-dXY!<9h_DRD-`S$*buHSYzCSiEdlT!Q+S}xXT0fn^yej1lO0c+--r+`wnS1 zhlvNz#}}jmd;1PqSTW~o9;~evwlInQGgueZf4p)dzUzZgfM|m&w`c>gq;htpfEbdL z3X+M*Pb@;++pbj*D%+AtOnt5&eCV0AU@mcSodd2d!R(;K0KS6YrUKM!8se#JZZj=&#DePEx3 zdk4=heC9za+1JYFIO!VtZNTvZto%Y0(}$tAVm~BY_^1)@3crZBX+_8Ov$cziZxgB0 z^1=^)Y1SX+U(dz&ZRlb$3gT;DWKTO$Qg21cV)%gUqeq|MJ4$Tapg4!#QN}z%-BzrR zkhNgnLn?-l#Hz@nO4<9}OmD;&pGJ5#_`w{xw zBBqvE@SdmJaS7EojMg)mxcrRyr$%i8Y=a*=z?YZ1wQ2?T8RRxx4Cek_8SO8@ztSK1 zeI%l8+_3jlOLt(mCAYg+b>iDhA7b63ITfm_ovKoPj_yGqvn69U8w^45uS6h%ah<0u|#5bJBjIpD7H}HRRFUbd2t(!E)+ir%Bg#_mT(9 zR14cCOdqv7ndWKFQDL0ExN~>Vu^HH(iv#4tZbwAE&B3xBq}~-{Q1F&6>&tBg0F#k8NKpSO)EkO$@=WKM8Xpcmj`s?#j0Xh5ezxABE@7z z93a!>?T62?@xflwA~tGV+O$TzB+4TF`MYCeg{)tgcv?rLm1uaVbOQD$^hZRY*IuU&yn!E)s1wt za0L!P4T*Q-Q((wpvy(|4pi?bj2gceYX%y=1+cUune$0$kCdwILtu}5y}f!7LtN55mll-!@g7D0EmqiU%(_!jux{^5$l-yye+ zVQq-7fcaO0ab$fVG%mbY`;;=--;P(bfK#7(KauN)MJ!v5!?V>&?tXgLT{*O$_G8X_ zqg0!o2U1*6N%bi6$~)ERm~YkR_KPnmzLfmm%k{fEAe_UjH8w+V5q46ZqRv~5i>->vx+dp7 zSPndLZuMIIT@p_1@($WTIE&9W?DHHrujNyjw* z@9hEnU0p#YYuLk3b_?nZe99ktT-)d595Ya=4tOVt;dbzF}O z2`5O~F_^$A@B>kXx7c1f1W?ClP zOMD7d?_#uEYJ9%o@=f|9jEH8qIy1`qswF%WTp9DPh7Nc53KT8HxGk!v{?*|;=375U zLq?l6!!S2;_Q}E3klQfrlQSuwgj2ZiQF5Kt?!X5Y;t;;~pbY3HK6M_D=XZwb{YZTQ zh$in2BOQJe(+2lmH--0_;-4ZO({;n&DV~Ro?f6eFT!787KT)T(#W>LTOm3sYIR07U zZPexHaXCCV97if4`WOPv_~E7EdkJ*TYE{(1-Slx6`mW3IJ$M_el%Zp1nNx9lfn&QS zhK=5*<=9mE=mJCH!Z|lQ3-~wqqTU9&d>}ABZ*tvYeZtuh4AR#YED_g(we-la+Dp%M zhq7Ns46wV**b?lB z_|L;Mfj-iAYK#rDe9G=B$)Z+_Pfg&O4Sg7xzL5uS`aS z?*jLT4)wYmulo9zsl)KO3w&*3p#GP;K~~^OT>OCB&((mAF6ryWG_C*|UxWq(W4xVq zFip6gAzbVrAD`WzExY4fT~6W^L`?3%Cque>KBiA<^ysnCH14~^3+E629>_>gjm51P z>dpGCcOm`1`8|*;LBM}{U+9Kk$AmF}IJ;1z;(H(mfmFzmein@r#AhnP|5v`Bumqj? zp6@4MvdUz_V*Vz`V^put2NYg9LgW2i-vl{1$p;kNP<~o((q*LY{T|3R{fpHG%e(YL zzv3*v9Wedp(Lvgx|Ax`GPhW?S`>!-g*od*Wb^23jLnhJraNvfVbopl5P}HX9;D1nP zg-O8%55DuJpai~Rt#S6D=3Li>B#c(r8HNE zewwaWUQslB2X15f>BV{UHJAO^woOp4oYh-$B0lp%b@+KH^ZQQ!De7(Y!v$sQkxk%V zg8D|gwAvHx#?}|C{XsvZ{kx8Be~@TDd@UJztlty1&*_(!UqtrZ=!4k*;{NVF>g z{(bsu*4u+rzK`CfLL|RiZ$~H4TUBS5(%64RXRHr@kp6b+<3WO$*u&pIJq2F~gf9pf z_iG!-_eu1w2yK1p4Y#4{h9g$rsrhe<@yDqu&YDWqJ;jk>@4;)c&}++k`6wA) z|0dH0Fj27yiovL%?Ns
YJgkpn++;71Pp$bla@@FNF)luYa^Ob}{K$d- zzd2x`Z%pBtUg@izWE(xc*_Pv*G`gVKwq(-iDqCYM`)#1#W)@{JJNwPYZ?4Ves&DlB znkNZ1E@)_|vz62~dHuD%Nt0@uJxeONo#vdz5w8T<<>)A#( zOBc_cHFNse#dGFNcg;jg&9;F8R6a{2MTf_F8ylqtzwhkx38g4Br&ts!am_B7=bCFP zQJf_+Y}1NeZfEJJfzr(4nWfVFS+k}2Gx0NX)?8`oylIkarnIEm>uYG5G|5xuX{xTQ zt84IjYU`V;n|zYwt*oza@Y%e8`>Mgqs!5Zos;}}_+v+Nt7FIXee2XgUZHp^gJk7P& zRAU$xR5sUoJ*ODK~^loRRY^X5vk=FO#mKZ&r`povMgh13DC)ZbiPWm`~P)6i6H ztE#T4t*`XeHq?(Lp}>>8KC0F>Gx{re4;aSpuh-Z>twyU>x70TKjH=*tWu2|Ly0Xc; z2m>_DHM7(v9g9}}(b5;Q_9U5aM@ClFsc zul(Oe8|{~%Kh`$}7>%?T9mr$DlIo_)g(L@K3u*>5R{DI^P4!4s4d7$SqV)|+DKu)W z*i=+o@3S#mGzlChNBH-G;8u?wo}y^GEtC^c3#HIpEd$kDKm9XnRCl{VB@Lr%(FlLm~Y zu0WZ2gb~D}bI3~ZsCQAd_ew&-^u#7Ko}+52ZYCRsz6rsb!XCpi+UEEm&CR}AZ?jG0 z2p;fM@?TgQ_FOycvFYz$({_R7B(28ro518}vWsyiZ!U}|o5EivYB3~lB z4dJ#lNqQdPr}z-fX*Z&Lx+I;4&<(t2-GuUkB*~62YltLW6o^F5!*{n{L)a)w($@$F z_#{kSA@E?NTd#7@9mLDDcbG8vD6~8YsX38 zdcfBr{1jm(4weg3C8-f%BSN~@@+`s*TxIzdp&hpbcB6jd?;;T!eLx3y7a!=4%ksDr zyA7{Rt$iBfk8~%(kqGV2L?Uw$Ha;JT6rq1bFF+;`wsuA$-3Zri0KKSZ-xP_oAne7L zcUsXOdl%Y8ScI?}VFkjED7`HbIgGIT#Yki&J`<~zeTtkvb=)edr=Qz zM-Rq{_>L<$jqK1-lJMP3_E@f&Em>MJEhi1`pH8>A2tE>j%FU6;IaH#wKdX_AXaWB0 zEzl8+k(7}+EhFnfdC=1IR_THhC!IAu`!qmV{mT#@hAfGu2+ZIOWYb$JT)F$aI8knfoYQ||^&JVbXEcS8+r+?{(2)ORKD-t;$xKj5)Nq{dz zV|FXiu{^ajBPWnHJ;R>z(!h)yKtKy0jSB}!rKsOZ^UX`A0ewV!***b z#&9`}d7vMWa?Lgax)4e^s!N3hv@C9?jsi z{X0B*fa=4xG9I1D>;ES_B3o_01DE{}rdm0k+f!W0^lN%XYl=0Tl8{Fj{e(Qa@$?vv zTH|??g*wEe7q7(F(35%_CO$mW*Ug|UXI&(+1@YAD0cU-^F!{I^rGzl5rN>xE z7uV@wn4{MKACuSd9N!O>SCaR+RR76HQ zqW~`V;AGKi`%I3lyA_VX$krRJDdOx4JW>Ri+0vNg}I*E`IXVm^eEqA z^8vGkG~e8tP#Z9!BqMGJZYO-76Y&2Mq+V&@L%+@Q7q~9wujv`x{jAmf5@JkdgGSk6 zGSb~IiHzt=B9YHPPwJhZ0T1b2Bccz$HjN{Il972an+@>lB9gZvZ_(3{$P_YU;Pq`L z`wjcc?6|q15Iya{cNzRo zrhEMjdVctP+D-L$iMirK2sj(he}6vBf{81D|6KrMmHGn5lX!fla~cfqH}6({!4xRwL<5n#+0L!WO= zfqN``p%kw%Pw@KW(-&@!M8GQckPfs1Rsh&ZXp4_y9M3V1R;#723ZN*-F%4c8))pV6 zgU&Z0UCb9O8Pc!xcI$1aN+|7CXsY#^l(CsrV+yC_n;1w*W=MX(}6hNeV6}-`gLzbBDFNe z`!Kn}J527|+;FV_2mPn>4tQ1rPfS|y>c`!~ zE$JfwIXA7zg0`1Y8+amj|HLvlEp4E6LfRzBh5Wd@p%?75+>v5=FeUBb6zQoHUVzmb zWf}3H1>f}Qv826|V%eXPb}&T>TB8N1OvF;qK~)}49e%egb@oT}tpTs5+%8L-2cH1Q zCxg=vzc(Wd@n;WD9f04Gw`c*osOYSQ`-$&QUmSM#xIVbIX zi$zUIgHYZZV;dnDa5Azt5)4n|Zt(GCOFcM~GU-mMu#k%+d#(9b)?Mpt+cb{xI?#f+gY;Q{1nh}y3XThczU5F<^}j&V7w0EVX9dSB`rL#0;-ykmKBsPyijsYt9CLMyXJ%)0&hX<#5$Gg*b%;G# z0+9jlJdVQ+y5|c-hA(Nfe~PGYl=~*a`v-nA5Zt=e&@kelj|1%jB>m-Db{%F4x0e?Z1pDD&mpp)Je@aqMjnH<0slkRfYaU!JvD$^q?4p9f!|n}?qu+hk}VEC0eVjON96MQ2A}T)JP{x65#{Z-@$$4E zKo2>!glDC|BiJD=?Z@Fy3plNp>A4Z`MEGwN<;#U%%S+=-UBFx8;P(r-;RhS#p9Gxv zY{;R(=dBEWtX_O3@UTq>0|~;fSovf1D+`WBBKni{YZS^`u&Ys;Kz|eAIS1wGKc+rtGvXLKaG8J`exT9i28QQYeGdXITq>g|3-3z;{|n%!K_0rN z^5X356VY7)-f=sJvwc8B{{V06IFy%e6PMj!HuKV!$(@M~3_eG?Fh#`6X~D6X9Q*q&yw#QNMbpbIi0aM^6vn ziSP`7g@2dQQdnGHjqf-ae0s3%+x(fB zr2OSc;MW3vny70IewC#BBMc5ZKZcj4Jw1BXCMo}R5_o<_;(j>+ADVKK6z_MS=`WDaj%&eQh^_yLG48^=W)-YMW#u#)6(+lw6D$^&T% z;EDJ@pUQ*IOktlP_U!So@{p5jdD_sIUjk0;+DkaRN3{E@C@I6JdJ^bmt{nE7`U zzN<-iS}QoTT4bhYgU*y={h0=oCwc1@^cZ{lw+MK9BS%2z5%l~~;4iA-X*z49XCD@F zAnBMV1?xDX$L8c&hFNbDXslE2e7k1MBh)+?w3j61L43V>aUZ*fqw$WPxmzF@d$W(K2NiIIf&kn1kc@o zlinHr2CoIXouvFOz}a{e^OEe|4WbudLxSMF6&z0Y1nB9PWV~KO`9%Gqg9gTDF~3;g z57CnW6UoN6il?{mKso~(9}KQ?fFXy&;KC-te+A%FUJ?pql)oAq42jDBEeU*xkcZwn z-Y(2Ldrk(N=A(Ffelf-;6Mjxkwg6P@L=IDqbe(DN39^LU?M^9u%^ zOJ>gT<>z}!>BheYSNp47t$n;<47|2lzJ@ES>zilK06Qjn zJl>X;{QUfJ=2snDUSgDYQDu|I*Hl^SYj$~^V3ODAbk3gRJD0y;;hIz6A@ccI5q+d$lr>Y4=~qHG&y zuWM!_?y0KuRnm(dc(o%Te+y7>0bX#p67Q7Y&b^aMj?r(^IE`a(L3sFE5X7$h@&5XT zrmE_u>MB5euJQ@f=*^uuzJf)S&5K-f#(A7`e1(un+~oH)@HE&8FeGw91K#YxOC5C{ z_I5;bU&;AzZEK=<`=F21{dcy&nYFmGw%!;9Fvspuzy)9Bf;woU;7mS~D`+GH6r)#F z?W_Dh?Onfb>&6`?nxI9eX6(?xTZbToWm}T9JzM6B6+ihIwqE0Axl$A@6A>weqHODr zDA27-hjhx2rBjd;Mf;YH9XfRC(xrQ+7F~*dzTdkqMII^J@k<69As`>gyYJoc?)&@h zdyXa@)fM-M=7$f2&)D%8!k3x@*r=ze3GBNL{ zB9-vFhN4Q$g-@9IQL2mWD1uTEVnKXFGEtSfEh;|rUJlgh(O^?y^x9w?;W!0)FqiU^ ztT&{hwQTFVq2|HLW(mPmV--vgMgwwIqp2ECrbA5O z2y;DG{^ABt9sK-wuixt;k0p%M0vT3(G0%L&*D1r=Up{|+ z<_*+fZ~uiywX%S_P{HNL&z`;iqPO2wTkf{I15N`mXI`D3EB)#YA$_prT@j0VGQ2}R zh*gosHiAJ(+3;zKM)IizF4*^HCEdj^jw1*Ru$^8Mc_gaOTEsnx3!Q}%#6vdbS($CJ z)LBU&DqGJr*E3DZsppw$JsfgUxI^=1s#~#kAM;}zTR^$r)u*lW2+KW$*V*Q=Fzze31 zF1SQ#C`|rJo4AFJhCCe2$3;Q8PTQ!O0@mOV$FT;d_Y%r4f|eD<6QelL9$1)NrqgST z=SXoFwG9N*!B;~FwL}Ge7F-qy7F?flDIl3_DbpPI{uW3%4&xx6S?{11a>L*%rr}AL zjI&D>QfM{I2dm43*I$=XNKfg&=2K{j$!JnG$(mw3 z7%Nk_bxEmxKrcz5Wo_{2tf{o2!5F!BUjhZ{<~lK>ad#boLK3gji8-sDKv7*Sfs#I) z6DUTZuRW&s_q_Z#jL|Z)g?4sr{W&Wpa^TsE)DqO zwjwlk_JG`;>h2JhLOFXiIf1dxMn#dJ4RAtC2et)FO$42;jGuRnLW&)F;8Iac)#>p=H3D*%kWnN%ZFqFNCY?X$w z;vR<44jVd9zJNrqE}>n&gyjyyc$O6Np;qSrBI{z)MoH^J)2si`~L;+4>_#>>gBp@MUX7cr9XT4|3@ z(U0UZnu(Ozg$UH96bTn{Fr^{aQv^ZIaE@|%NkW@{_YizF!<`cergy#DU3*WNDLfvB zJ7zm~mhSX`h&6IwO`>6-g872Q@cl8cX2uJO0$G2&lw_0`C{k~-MovagjAQi7^cfGM zMvgEc;aK%dR;~6j{tzwPvCx1O1Dtb68X^P()MET_Se^7Dr#Mt}+m4eJv6Q6p<8@)_ z59$s2ShbhsPUv~G*g2pzen-7ZuCYNyo#N=fn1-v{#k!x_S@RHgu0G4tJGJE#Eq$yI zm=;Sl0zagUctLYZ*7s3hi9x->BK*nP%Yzo-qaKGDZM&&k0@9mmc$0`(FEYzTSUlZ? z7p<*MfkA7!O#5$|YCz7RI#;%~{O!f7+iCNg-0mU6&wLnrsiMRp(W=Q<(YhX^XF`*J z8pqQ_%OF}V#RKvTt zI>!;br3Zz)G@SSZVD4s<%yCH$IxcSA@zmVR!@zOjvcV%WEjOL=va%aqnmrwtBh)5O zXeNMj_a+Eunc{6!x>mh2MAsqrR1b9nRdSd8I6_;xc4$lvHm}4n_L7u#P(J7ZJDnZc ziuyeR{o}XvjieHnZnC+o+*68eupA>U@Vf?H(hVw9xFp^}UbS%Z1N;R3+`vnUZLp>5 z?a~we?=GH;@Dfie>4sI_hW`-x|3)miv@h}Yl0Gx=-#4k&nC9?i^Yd$y%6S0NzQD`(|JuOsn+he)SW-EUfZ*xO1RMUh zct_(Z^*bAQplgHw(oX);WzYX_kXwY`*wDo#<+EiAHDHH6Uy^=?ry{(>H|MD-FNwfO z`a26=;-Dq{hYYN#K;R_(%7T}8T}l7;v9zpHfs?m?vf$DxS{bAc!|T5l+J=KUUvI`M`jUT;<+XL72?c_m*9`Q`zLOS@Dlee z>Aws=lJa)@|3L;dA;l!l^YHf?!X9sFU(&bGI6~fXc!?uFH}FzU*S5lcdH*B8Q~#xX zi8ud+fu~b`iq}T*0r&Jz!HISRUgFYs|DX%LV$X?}vCNeb*5B@0Wko>HmIOe7kB_-ct2-@L&8_ Nm*_}G4S@CN{2xg8(e3~M diff --git a/circuit.cpp b/circuit.cpp index a9f0d62..44c5d50 100644 --- a/circuit.cpp +++ b/circuit.cpp @@ -7,12 +7,9 @@ void Circuit::init_stems() { for(auto& gate: gates) { - if(rand() % 10 <= 2) { + if(gate->outputs.size() >= 2) { gate->stem = true; } - // if(gate->outputs.size() >= 3) { - - // } if(gate->stem) { stems.push_back(gate); } diff --git a/circuit.h b/circuit.h index e02277e..5f1447c 100644 --- a/circuit.h +++ b/circuit.h @@ -78,7 +78,7 @@ int* flip_need_update; std::vector flip_update_queue; // incremental stem struct -const int STEM_INC = 100; +int STEM_INC = 0; const int STEM_WEIGHT_MAX = 1e9; ll stem_total_weight; int stem_total_cnt; diff --git a/ls.cpp b/ls.cpp index c466106..916f99d 100644 --- a/ls.cpp +++ b/ls.cpp @@ -8,6 +8,8 @@ bool Circuit::local_search(std::unordered_set &faults) { + STEM_INC = 0; + // 初始化并重置所有 ls 数据结构 ls_init_data_structs(); @@ -51,8 +53,8 @@ bool Circuit::local_search(std::unordered_set &faults) { } if(max_score > 0) { - // printf("FLIP: %s\n", stem->name.c_str()); - printf("[LS] flip: %lld, stem: %lld, fault:%lld. flip_cnt: %d, stem_cnt: %d, fault_cnt:%d\n", flip_total_weight, stem_total_weight, fault_total_weight, flip_total_cnt, stem_total_cnt, fault_total_cnt); + // printf("FLIP: %s (+%lld)\n", stem->name.c_str(), max_score); + // printf("[LS] flip: %lld, stem: %lld, fault:%lld. flip_cnt: %d, stem_cnt: %d, fault_cnt:%d\n", flip_total_weight, stem_total_weight, fault_total_weight, flip_total_cnt, stem_total_cnt, fault_total_cnt); ls_flip(stem); CC[stem->id] = 0; @@ -123,7 +125,6 @@ bool Circuit::local_search(std::unordered_set &faults) { ls_update(g); } - static int original_faults = -1; if(original_faults == - 1) { original_faults = faults.size(); @@ -148,20 +149,23 @@ bool Circuit::local_search(std::unordered_set &faults) { } void Circuit::ls_update_weight() { + + STEM_INC++; + if(rand() % 10000 <= SP * 10000) { - // for(Gate* g : gates) { - // if(g->stem && stem_satisfied[g->id] && (stem_weight[g->id] - STEM_INC >= 1)) { - // stem_weight[g->id] -= STEM_INC; - // for(Gate* suc : g->suc_stems) { - // if(stem_weight[suc->id] + STEM_INC <= STEM_WEIGHT_MAX) { - // stem_weight[suc->id] += STEM_INC; - // if(!stem_satisfied[suc->id]) { - // stem_total_weight += STEM_INC; - // } - // } - // } - // } - // } + for(Gate* g : gates) { + if(g->stem && stem_satisfied[g->id] && (stem_weight[g->id] - STEM_INC >= 1)) { + stem_weight[g->id] -= STEM_INC; + for(Gate* suc : g->suc_stems) { + if(stem_weight[suc->id] + STEM_INC <= STEM_WEIGHT_MAX) { + stem_weight[suc->id] += STEM_INC; + if(!stem_satisfied[suc->id]) { + stem_total_weight += STEM_INC; + } + } + } + } + } } else { for(Gate* g : gates) { if(flip_need_update[g->id] && (flip_weight[g->id] + FLIP_INC < FLIP_WEIGHT_MAX)) { @@ -181,14 +185,23 @@ void Circuit::ls_update_weight() { } } } + } - for(Gate* pre : g->pre_stems) { - if(stem_weight[pre->id] + STEM_INC < STEM_WEIGHT_MAX) { - stem_weight[pre->id] += STEM_INC; - if(!stem_satisfied[pre->id]) { - stem_total_weight += STEM_INC; - } + for(int i=0; i<=1; i++) { + if(!fault_weight[g->id][i]) continue; + for(Gate* suc : g->suc_stems) { + int inc = std::max(1, fault_weight[g->id][i]); + + if(fault_weight[suc->id][0] + inc <= FAULT_WEIGHT_MAX) { + fault_weight[suc->id][0] += inc; + if(suc->sa[0]) fault_total_weight += inc; } + + if(fault_weight[suc->id][1] + inc <= FAULT_WEIGHT_MAX) { + fault_weight[suc->id][1] += inc; + if(suc->sa[1]) fault_total_weight += inc; + } + } } @@ -217,18 +230,21 @@ void Circuit::ls_update(Gate* stem) { } ll Circuit::ls_pick_score(Gate* stem) { + ll old_score = ls_score(); + ls_flip(stem); ll new_score = ls_score(); ls_flip(stem); - ll old_score = ls_score(); + old_score = std::max(old_score, ls_score()); return new_score - old_score; } ll Circuit::ls_score() { + //ll score = -flip_total_weight -stem_total_weight + fault_total_weight; ll score = -flip_total_weight -stem_total_weight + fault_total_weight; return score; } diff --git a/output.txt b/output.txt new file mode 100644 index 0000000..6e8897d --- /dev/null +++ b/output.txt @@ -0,0 +1,9702 @@ +set -e; rm -f parser.d; g++ -MM -O3 -std=c++17 parser.cpp > parser.d.$$; sed 's,\(parser\)\.o[ :]*,\1.o parser.d : ,g' < parser.d.$$ > parser.d; rm -f parser.d.$$ +set -e; rm -f main.d; g++ -MM -O3 -std=c++17 main.cpp > main.d.$$; sed 's,\(main\)\.o[ :]*,\1.o main.d : ,g' < main.d.$$ > main.d; rm -f main.d.$$ +set -e; rm -f ls.d; g++ -MM -O3 -std=c++17 ls.cpp > ls.d.$$; sed 's,\(ls\)\.o[ :]*,\1.o ls.d : ,g' < ls.d.$$ > ls.d; rm -f ls.d.$$ +set -e; rm -f gate.d; g++ -MM -O3 -std=c++17 gate.cpp > gate.d.$$; sed 's,\(gate\)\.o[ :]*,\1.o gate.d : ,g' < gate.d.$$ > gate.d; rm -f gate.d.$$ +set -e; rm -f circuit.d; g++ -MM -O3 -std=c++17 circuit.cpp > circuit.d.$$; sed 's,\(circuit\)\.o[ :]*,\1.o circuit.d : ,g' < circuit.d.$$ > circuit.d; rm -f circuit.d.$$ +g++ -O3 -std=c++17 -c circuit.cpp -o circuit.o +g++ -O3 -std=c++17 -c gate.cpp -o gate.o +g++ -O3 -std=c++17 -c ls.cpp -o ls.o +g++ -O3 -std=c++17 -c main.cpp -o main.o +g++ -O3 -std=c++17 -c parser.cpp -o parser.o +g++ -O3 -std=c++17 circuit.o gate.o ls.o main.o parser.o -o atpg +======================== +parsing file c432.bench ... Done. +====== Circuit Statistics ====== +PI: 36 +PO: 7 +Gate: 196 +Stem: 96 +================================ +local search! +[UP] flip: 3, stem: 23, fault:334. flip_cnt: 2, stem_cnt: 84, fault_cnt:78 +[UP] flip: 6, stem: 35, fault:396. flip_cnt: 2, stem_cnt: 87, fault_cnt:78 +[UP] flip: 4, stem: 24, fault:680. flip_cnt: 1, stem_cnt: 90, fault_cnt:71 +[UP] flip: 0, stem: 17, fault:742. flip_cnt: 0, stem_cnt: 93, fault_cnt:73 +[UP] flip: 14, stem: 19, fault:711. flip_cnt: 3, stem_cnt: 90, fault_cnt:62 +[UP] flip: 7, stem: 19, fault:740. flip_cnt: 1, stem_cnt: 94, fault_cnt:69 +[UP] flip: 14, stem: 36, fault:893. flip_cnt: 4, stem_cnt: 92, fault_cnt:77 +[UP] flip: 7, stem: 36, fault:934. flip_cnt: 1, stem_cnt: 93, fault_cnt:80 +[UP] flip: 6, stem: 54, fault:952. flip_cnt: 1, stem_cnt: 93, fault_cnt:79 +[UP] flip: 287, stem: 72, fault:705. flip_cnt: 31, stem_cnt: 92, fault_cnt:62 +[UP] flip: 54, stem: 58, fault:589. flip_cnt: 7, stem_cnt: 94, fault_cnt:52 +[UP] flip: 11, stem: 59, fault:509. flip_cnt: 1, stem_cnt: 94, fault_cnt:43 +[UP] flip: 21, stem: 73, fault:423. flip_cnt: 2, stem_cnt: 93, fault_cnt:32 +[UP] flip: 0, stem: 26, fault:1239. flip_cnt: 0, stem_cnt: 95, fault_cnt:94 +[UP] flip: 29, stem: 45, fault:1553. flip_cnt: 2, stem_cnt: 94, fault_cnt:110 +[UP] flip: 167, stem: 32, fault:1059. flip_cnt: 14, stem_cnt: 94, fault_cnt:74 +[UP] flip: 30, stem: 178, fault:1487. flip_cnt: 2, stem_cnt: 88, fault_cnt:105 +[UP] flip: 29, stem: 268, fault:1421. flip_cnt: 2, stem_cnt: 89, fault_cnt:100 +[UP] flip: 0, stem: 308, fault:1342. flip_cnt: 0, stem_cnt: 90, fault_cnt:94 +[UP] flip: 31, stem: 350, fault:1302. flip_cnt: 2, stem_cnt: 91, fault_cnt:91 +[UP] flip: 52, stem: 372, fault:1270. flip_cnt: 3, stem_cnt: 90, fault_cnt:87 +[UP] flip: 35, stem: 406, fault:1299. flip_cnt: 2, stem_cnt: 90, fault_cnt:87 +[UP] flip: 36, stem: 404, fault:1337. flip_cnt: 2, stem_cnt: 90, fault_cnt:87 +[UP] flip: 20, stem: 363, fault:1191. flip_cnt: 1, stem_cnt: 93, fault_cnt:79 +[UP] flip: 40, stem: 193, fault:1148. flip_cnt: 2, stem_cnt: 95, fault_cnt:76 +[UP] flip: 102, stem: 0, fault:1098. flip_cnt: 5, stem_cnt: 96, fault_cnt:72 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:1155. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 0.1888 pattern: 1 before: 392 now: 318 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 233, fault:297. flip_cnt: 4, stem_cnt: 87, fault_cnt:37 +[UP] flip: 5, stem: 180, fault:770. flip_cnt: 2, stem_cnt: 90, fault_cnt:86 +[UP] flip: 17, stem: 91, fault:758. flip_cnt: 9, stem_cnt: 92, fault_cnt:90 +[UP] flip: 23, stem: 130, fault:752. flip_cnt: 7, stem_cnt: 85, fault_cnt:89 +[UP] flip: 4, stem: 132, fault:781. flip_cnt: 1, stem_cnt: 92, fault_cnt:83 +[UP] flip: 9, stem: 102, fault:848. flip_cnt: 2, stem_cnt: 93, fault_cnt:81 +[UP] flip: 5, stem: 141, fault:859. flip_cnt: 1, stem_cnt: 91, fault_cnt:78 +[UP] flip: 36, stem: 71, fault:809. flip_cnt: 5, stem_cnt: 94, fault_cnt:69 +[UP] flip: 8, stem: 66, fault:824. flip_cnt: 1, stem_cnt: 94, fault_cnt:69 +[UP] flip: 8, stem: 78, fault:820. flip_cnt: 1, stem_cnt: 92, fault_cnt:68 +[UP] flip: 9, stem: 145, fault:810. flip_cnt: 1, stem_cnt: 92, fault_cnt:67 +[UP] flip: 0, stem: 0, fault:1030. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:1030. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 0.3724 pattern: 2 before: 318 now: 246 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 169, fault:428. flip_cnt: 0, stem_cnt: 91, fault_cnt:69 +[UP] flip: 32, stem: 264, fault:760. flip_cnt: 13, stem_cnt: 83, fault_cnt:96 +[UP] flip: 3, stem: 176, fault:859. flip_cnt: 1, stem_cnt: 92, fault_cnt:105 +[UP] flip: 5, stem: 91, fault:873. flip_cnt: 1, stem_cnt: 93, fault_cnt:102 +[UP] flip: 22, stem: 179, fault:877. flip_cnt: 4, stem_cnt: 93, fault_cnt:104 +[UP] flip: 45, stem: 137, fault:763. flip_cnt: 7, stem_cnt: 92, fault_cnt:93 +[UP] flip: 54, stem: 184, fault:699. flip_cnt: 8, stem_cnt: 93, fault_cnt:66 +[UP] flip: 37, stem: 194, fault:748. flip_cnt: 5, stem_cnt: 93, fault_cnt:79 +[UP] flip: 0, stem: 143, fault:765. flip_cnt: 0, stem_cnt: 93, fault_cnt:82 +[UP] flip: 8, stem: 102, fault:735. flip_cnt: 1, stem_cnt: 94, fault_cnt:81 +[UP] flip: 45, stem: 0, fault:736. flip_cnt: 5, stem_cnt: 96, fault_cnt:79 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:799. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 0.4541 pattern: 3 before: 246 now: 214 +checking valid circuit ... result: 1. +local search! +[UP] flip: 24, stem: 162, fault:262. flip_cnt: 12, stem_cnt: 93, fault_cnt:41 +[UP] flip: 21, stem: 220, fault:380. flip_cnt: 7, stem_cnt: 92, fault_cnt:50 +[UP] flip: 23, stem: 334, fault:744. flip_cnt: 9, stem_cnt: 90, fault_cnt:114 +[UP] flip: 46, stem: 176, fault:664. flip_cnt: 15, stem_cnt: 85, fault_cnt:103 +[UP] flip: 11, stem: 400, fault:813. flip_cnt: 2, stem_cnt: 90, fault_cnt:95 +[UP] flip: 43, stem: 403, fault:760. flip_cnt: 7, stem_cnt: 91, fault_cnt:89 +[UP] flip: 0, stem: 359, fault:697. flip_cnt: 0, stem_cnt: 90, fault_cnt:77 +[UP] flip: 0, stem: 60, fault:729. flip_cnt: 0, stem_cnt: 95, fault_cnt:83 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:732. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 0.5204 pattern: 4 before: 214 now: 188 +checking valid circuit ... result: 1. +local search! +[UP] flip: 29, stem: 380, fault:182. flip_cnt: 23, stem_cnt: 88, fault_cnt:21 +[UP] flip: 6, stem: 320, fault:493. flip_cnt: 3, stem_cnt: 91, fault_cnt:83 +[UP] flip: 35, stem: 196, fault:671. flip_cnt: 11, stem_cnt: 92, fault_cnt:105 +[UP] flip: 65, stem: 66, fault:721. flip_cnt: 15, stem_cnt: 94, fault_cnt:107 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:756. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 0.5995 pattern: 5 before: 188 now: 157 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 417, fault:213. flip_cnt: 0, stem_cnt: 81, fault_cnt:27 +[UP] flip: 10, stem: 484, fault:652. flip_cnt: 4, stem_cnt: 88, fault_cnt:78 +[UP] flip: 2, stem: 210, fault:701. flip_cnt: 1, stem_cnt: 93, fault_cnt:75 +[UP] flip: 60, stem: 141, fault:666. flip_cnt: 15, stem_cnt: 94, fault_cnt:64 +[UP] flip: 34, stem: 217, fault:705. flip_cnt: 8, stem_cnt: 92, fault_cnt:62 +[UP] flip: 4, stem: 220, fault:681. flip_cnt: 1, stem_cnt: 92, fault_cnt:63 +[UP] flip: 94, stem: 293, fault:669. flip_cnt: 16, stem_cnt: 92, fault_cnt:56 +[UP] flip: 206, stem: 68, fault:587. flip_cnt: 24, stem_cnt: 95, fault_cnt:63 +[UP] flip: 65, stem: 140, fault:458. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 68, stem: 225, fault:409. flip_cnt: 7, stem_cnt: 93, fault_cnt:43 +[UP] flip: 41, stem: 154, fault:474. flip_cnt: 4, stem_cnt: 95, fault_cnt:46 +[UP] flip: 0, stem: 310, fault:569. flip_cnt: 0, stem_cnt: 94, fault_cnt:53 +[UP] flip: 0, stem: 389, fault:570. flip_cnt: 0, stem_cnt: 94, fault_cnt:53 +[UP] flip: 53, stem: 391, fault:477. flip_cnt: 4, stem_cnt: 95, fault_cnt:46 +[UP] flip: 0, stem: 0, fault:540. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:540. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.6429 pattern: 6 before: 157 now: 140 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 337, fault:274. flip_cnt: 0, stem_cnt: 91, fault_cnt:49 +[UP] flip: 8, stem: 340, fault:353. flip_cnt: 3, stem_cnt: 92, fault_cnt:47 +[UP] flip: 0, stem: 256, fault:428. flip_cnt: 0, stem_cnt: 93, fault_cnt:50 +[UP] flip: 19, stem: 343, fault:389. flip_cnt: 5, stem_cnt: 93, fault_cnt:46 +[UP] flip: 16, stem: 354, fault:363. flip_cnt: 3, stem_cnt: 85, fault_cnt:46 +[UP] flip: 50, stem: 268, fault:520. flip_cnt: 15, stem_cnt: 92, fault_cnt:65 +[UP] flip: 0, stem: 181, fault:540. flip_cnt: 0, stem_cnt: 93, fault_cnt:44 +[UP] flip: 46, stem: 92, fault:462. flip_cnt: 7, stem_cnt: 94, fault_cnt:46 +[UP] flip: 0, stem: 92, fault:559. flip_cnt: 0, stem_cnt: 95, fault_cnt:54 +[UP] flip: 80, stem: 277, fault:559. flip_cnt: 9, stem_cnt: 92, fault_cnt:54 +[UP] flip: 66, stem: 369, fault:466. flip_cnt: 7, stem_cnt: 94, fault_cnt:45 +[UP] flip: 14, stem: 755, fault:636. flip_cnt: 2, stem_cnt: 93, fault_cnt:50 +[UP] flip: 67, stem: 2252, fault:494. flip_cnt: 7, stem_cnt: 94, fault_cnt:42 +[UP] flip: 105, stem: 2066, fault:553. flip_cnt: 10, stem_cnt: 95, fault_cnt:47 +[UP] flip: 81, stem: 2525, fault:537. flip_cnt: 7, stem_cnt: 94, fault_cnt:45 +[UP] flip: 33, stem: 458, fault:542. flip_cnt: 3, stem_cnt: 95, fault_cnt:59 +[UP] flip: 29, stem: 359, fault:542. flip_cnt: 3, stem_cnt: 95, fault_cnt:59 +[UP] flip: 13, stem: 185, fault:561. flip_cnt: 1, stem_cnt: 95, fault_cnt:62 +[UP] flip: 36, stem: 158, fault:542. flip_cnt: 3, stem_cnt: 95, fault_cnt:59 +[UP] flip: 75, stem: 56, fault:581. flip_cnt: 5, stem_cnt: 95, fault_cnt:63 +[UP] flip: 155, stem: 164, fault:522. flip_cnt: 9, stem_cnt: 93, fault_cnt:58 +[UP] flip: 16, stem: 619, fault:734. flip_cnt: 1, stem_cnt: 94, fault_cnt:60 +[UP] flip: 32, stem: 397, fault:754. flip_cnt: 2, stem_cnt: 94, fault_cnt:63 +[UP] flip: 19, stem: 397, fault:734. flip_cnt: 1, stem_cnt: 95, fault_cnt:60 +[UP] flip: 18, stem: 255, fault:678. flip_cnt: 1, stem_cnt: 93, fault_cnt:54 +[UP] flip: 514, stem: 904, fault:845. flip_cnt: 27, stem_cnt: 92, fault_cnt:59 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:832. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 0.6888 pattern: 7 before: 140 now: 122 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 335, fault:337. flip_cnt: 2, stem_cnt: 91, fault_cnt:38 +[UP] flip: 0, stem: 113, fault:378. flip_cnt: 0, stem_cnt: 94, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:438. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.7474 pattern: 8 before: 122 now: 99 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 342, fault:334. flip_cnt: 1, stem_cnt: 93, fault_cnt:78 +[UP] flip: 0, stem: 575, fault:387. flip_cnt: 0, stem_cnt: 91, fault_cnt:78 +[UP] flip: 37, stem: 464, fault:306. flip_cnt: 10, stem_cnt: 91, fault_cnt:36 +[UP] flip: 41, stem: 347, fault:238. flip_cnt: 9, stem_cnt: 92, fault_cnt:24 +[UP] flip: 5, stem: 589, fault:452. flip_cnt: 1, stem_cnt: 89, fault_cnt:65 +[UP] flip: 0, stem: 594, fault:643. flip_cnt: 0, stem_cnt: 91, fault_cnt:74 +[UP] flip: 18, stem: 240, fault:454. flip_cnt: 3, stem_cnt: 94, fault_cnt:61 +[UP] flip: 156, stem: 238, fault:309. flip_cnt: 22, stem_cnt: 94, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:382. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 0.7526 pattern: 9 before: 99 now: 97 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 615, fault:217. flip_cnt: 1, stem_cnt: 91, fault_cnt:46 +[UP] flip: 11, stem: 497, fault:412. flip_cnt: 4, stem_cnt: 91, fault_cnt:68 +[UP] flip: 60, stem: 2, fault:519. flip_cnt: 16, stem_cnt: 94, fault_cnt:74 +[UP] flip: 38, stem: 129, fault:518. flip_cnt: 9, stem_cnt: 92, fault_cnt:68 +[UP] flip: 12, stem: 261, fault:497. flip_cnt: 3, stem_cnt: 86, fault_cnt:67 +[UP] flip: 20, stem: 0, fault:541. flip_cnt: 3, stem_cnt: 96, fault_cnt:65 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:542. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 0.7628 pattern: 10 before: 97 now: 93 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 521, fault:250. flip_cnt: 0, stem_cnt: 91, fault_cnt:28 +[UP] flip: 5, stem: 524, fault:507. flip_cnt: 2, stem_cnt: 91, fault_cnt:67 +[UP] flip: 44, stem: 396, fault:672. flip_cnt: 15, stem_cnt: 92, fault_cnt:85 +[UP] flip: 29, stem: 926, fault:638. flip_cnt: 7, stem_cnt: 90, fault_cnt:72 +[UP] flip: 5, stem: 532, fault:797. flip_cnt: 1, stem_cnt: 92, fault_cnt:87 +[UP] flip: 9, stem: 398, fault:861. flip_cnt: 2, stem_cnt: 94, fault_cnt:95 +[UP] flip: 0, stem: 533, fault:833. flip_cnt: 0, stem_cnt: 93, fault_cnt:96 +[UP] flip: 72, stem: 401, fault:802. flip_cnt: 11, stem_cnt: 87, fault_cnt:95 +[UP] flip: 0, stem: 1230, fault:864. flip_cnt: 0, stem_cnt: 88, fault_cnt:82 +[UP] flip: 66, stem: 392, fault:863. flip_cnt: 9, stem_cnt: 93, fault_cnt:95 +[UP] flip: 90, stem: 1087, fault:836. flip_cnt: 11, stem_cnt: 86, fault_cnt:85 +[UP] flip: 17, stem: 978, fault:869. flip_cnt: 2, stem_cnt: 90, fault_cnt:76 +[UP] flip: 420, stem: 426, fault:755. flip_cnt: 37, stem_cnt: 92, fault_cnt:67 +[UP] flip: 9, stem: 425, fault:746. flip_cnt: 1, stem_cnt: 94, fault_cnt:99 +[UP] flip: 101, stem: 701, fault:695. flip_cnt: 7, stem_cnt: 93, fault_cnt:93 +[UP] flip: 29, stem: 138, fault:775. flip_cnt: 2, stem_cnt: 95, fault_cnt:108 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:772. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 0.7704 pattern: 11 before: 93 now: 90 +checking valid circuit ... result: 1. +local search! +[UP] flip: 47, stem: 885, fault:312. flip_cnt: 27, stem_cnt: 87, fault_cnt:33 +[UP] flip: 3, stem: 444, fault:465. flip_cnt: 1, stem_cnt: 93, fault_cnt:57 +[UP] flip: 28, stem: 1, fault:496. flip_cnt: 8, stem_cnt: 95, fault_cnt:57 +[UP] flip: 32, stem: 298, fault:462. flip_cnt: 7, stem_cnt: 93, fault_cnt:48 +[UP] flip: 34, stem: 148, fault:469. flip_cnt: 7, stem_cnt: 94, fault_cnt:53 +[UP] flip: 41, stem: 148, fault:474. flip_cnt: 7, stem_cnt: 94, fault_cnt:53 +[UP] flip: 25, stem: 2, fault:500. flip_cnt: 4, stem_cnt: 94, fault_cnt:53 +[UP] flip: 232, stem: 156, fault:466. flip_cnt: 37, stem_cnt: 93, fault_cnt:51 +[UP] flip: 26, stem: 302, fault:595. flip_cnt: 4, stem_cnt: 94, fault_cnt:82 +[UP] flip: 30, stem: 147, fault:605. flip_cnt: 4, stem_cnt: 95, fault_cnt:84 +[UP] flip: 38, stem: 147, fault:605. flip_cnt: 4, stem_cnt: 95, fault_cnt:85 +[UP] flip: 96, stem: 296, fault:605. flip_cnt: 9, stem_cnt: 93, fault_cnt:90 +[UP] flip: 12, stem: 460, fault:698. flip_cnt: 1, stem_cnt: 94, fault_cnt:84 +[UP] flip: 413, stem: 467, fault:678. flip_cnt: 37, stem_cnt: 93, fault_cnt:83 +[UP] flip: 7, stem: 323, fault:718. flip_cnt: 1, stem_cnt: 93, fault_cnt:80 +[UP] flip: 44, stem: 0, fault:804. flip_cnt: 4, stem_cnt: 96, fault_cnt:92 +[UP] flip: 48, stem: 0, fault:804. flip_cnt: 4, stem_cnt: 96, fault_cnt:92 +[UP] flip: 65, stem: 1, fault:804. flip_cnt: 5, stem_cnt: 95, fault_cnt:89 +[UP] flip: 379, stem: 140, fault:777. flip_cnt: 24, stem_cnt: 95, fault_cnt:89 +[UP] flip: 142, stem: 441, fault:682. flip_cnt: 9, stem_cnt: 93, fault_cnt:73 +[UP] flip: 123, stem: 152, fault:574. flip_cnt: 7, stem_cnt: 95, fault_cnt:61 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:745. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 0.7934 pattern: 12 before: 90 now: 81 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 677, fault:307. flip_cnt: 4, stem_cnt: 91, fault_cnt:46 +[UP] flip: 19, stem: 680, fault:460. flip_cnt: 9, stem_cnt: 91, fault_cnt:67 +[UP] flip: 0, stem: 512, fault:474. flip_cnt: 0, stem_cnt: 93, fault_cnt:54 +[UP] flip: 13, stem: 351, fault:460. flip_cnt: 3, stem_cnt: 86, fault_cnt:52 +[UP] flip: 0, stem: 520, fault:504. flip_cnt: 0, stem_cnt: 92, fault_cnt:51 +[UP] flip: 62, stem: 173, fault:458. flip_cnt: 11, stem_cnt: 95, fault_cnt:56 +[UP] flip: 0, stem: 176, fault:501. flip_cnt: 0, stem_cnt: 94, fault_cnt:65 +[UP] flip: 0, stem: 1, fault:507. flip_cnt: 0, stem_cnt: 95, fault_cnt:61 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:507. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 0.8087 pattern: 13 before: 81 now: 75 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 713, fault:214. flip_cnt: 9, stem_cnt: 91, fault_cnt:59 +[UP] flip: 3, stem: 1432, fault:386. flip_cnt: 1, stem_cnt: 88, fault_cnt:83 +[UP] flip: 22, stem: 362, fault:513. flip_cnt: 9, stem_cnt: 89, fault_cnt:102 +[UP] flip: 0, stem: 903, fault:400. flip_cnt: 0, stem_cnt: 91, fault_cnt:50 +[UP] flip: 6, stem: 365, fault:494. flip_cnt: 2, stem_cnt: 93, fault_cnt:67 +[UP] flip: 33, stem: 182, fault:455. flip_cnt: 7, stem_cnt: 94, fault_cnt:58 +[UP] flip: 36, stem: 181, fault:458. flip_cnt: 7, stem_cnt: 95, fault_cnt:59 +[UP] flip: 41, stem: 551, fault:446. flip_cnt: 7, stem_cnt: 93, fault_cnt:53 +[UP] flip: 44, stem: 367, fault:443. flip_cnt: 7, stem_cnt: 94, fault_cnt:58 +[UP] flip: 23, stem: 0, fault:489. flip_cnt: 4, stem_cnt: 96, fault_cnt:61 +[UP] flip: 78, stem: 179, fault:525. flip_cnt: 8, stem_cnt: 95, fault_cnt:54 +[UP] flip: 32, stem: 559, fault:600. flip_cnt: 4, stem_cnt: 93, fault_cnt:62 +[UP] flip: 63, stem: 181, fault:491. flip_cnt: 7, stem_cnt: 95, fault_cnt:58 +[UP] flip: 21, stem: 1, fault:527. flip_cnt: 2, stem_cnt: 95, fault_cnt:63 +[UP] flip: 100, stem: 181, fault:519. flip_cnt: 10, stem_cnt: 95, fault_cnt:57 +[UP] flip: 82, stem: 360, fault:483. flip_cnt: 7, stem_cnt: 94, fault_cnt:55 +[UP] flip: 47, stem: 182, fault:503. flip_cnt: 4, stem_cnt: 94, fault_cnt:55 +[UP] flip: 486, stem: 378, fault:467. flip_cnt: 37, stem_cnt: 93, fault_cnt:53 +[UP] flip: 52, stem: 179, fault:560. flip_cnt: 4, stem_cnt: 95, fault_cnt:75 +[UP] flip: 54, stem: 179, fault:613. flip_cnt: 4, stem_cnt: 95, fault_cnt:85 +[UP] flip: 64, stem: 179, fault:613. flip_cnt: 4, stem_cnt: 95, fault_cnt:85 +[UP] flip: 68, stem: 179, fault:613. flip_cnt: 4, stem_cnt: 95, fault_cnt:85 +[UP] flip: 170, stem: 356, fault:599. flip_cnt: 9, stem_cnt: 93, fault_cnt:84 +[UP] flip: 19, stem: 571, fault:740. flip_cnt: 1, stem_cnt: 94, fault_cnt:82 +[UP] flip: 714, stem: 565, fault:696. flip_cnt: 37, stem_cnt: 93, fault_cnt:81 +[UP] flip: 115, stem: 181, fault:642. flip_cnt: 9, stem_cnt: 94, fault_cnt:66 +[UP] flip: 35, stem: 394, fault:645. flip_cnt: 2, stem_cnt: 92, fault_cnt:64 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:915. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 0.8444 pattern: 14 before: 75 now: 61 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 826, fault:247. flip_cnt: 9, stem_cnt: 90, fault_cnt:39 +[UP] flip: 2, stem: 207, fault:626. flip_cnt: 1, stem_cnt: 95, fault_cnt:84 +[UP] flip: 7, stem: 417, fault:707. flip_cnt: 2, stem_cnt: 93, fault_cnt:83 +[UP] flip: 15, stem: 833, fault:451. flip_cnt: 3, stem_cnt: 92, fault_cnt:64 +[UP] flip: 40, stem: 841, fault:386. flip_cnt: 7, stem_cnt: 91, fault_cnt:50 +[UP] flip: 0, stem: 421, fault:457. flip_cnt: 0, stem_cnt: 94, fault_cnt:55 +[UP] flip: 0, stem: 422, fault:439. flip_cnt: 0, stem_cnt: 92, fault_cnt:46 +[UP] flip: 0, stem: 424, fault:427. flip_cnt: 0, stem_cnt: 94, fault_cnt:46 +[UP] flip: 183, stem: 212, fault:425. flip_cnt: 23, stem_cnt: 95, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:464. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.8622 pattern: 15 before: 61 now: 54 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 865, fault:200. flip_cnt: 2, stem_cnt: 91, fault_cnt:27 +[UP] flip: 0, stem: 867, fault:266. flip_cnt: 0, stem_cnt: 92, fault_cnt:36 +[UP] flip: 0, stem: 655, fault:449. flip_cnt: 0, stem_cnt: 92, fault_cnt:60 +[UP] flip: 0, stem: 439, fault:537. flip_cnt: 0, stem_cnt: 93, fault_cnt:62 +[UP] flip: 43, stem: 221, fault:452. flip_cnt: 10, stem_cnt: 94, fault_cnt:46 +[UP] flip: 10, stem: 220, fault:463. flip_cnt: 2, stem_cnt: 95, fault_cnt:53 +[UP] flip: 7, stem: 886, fault:409. flip_cnt: 1, stem_cnt: 92, fault_cnt:46 +[UP] flip: 92, stem: 1, fault:467. flip_cnt: 15, stem_cnt: 95, fault_cnt:50 +[UP] flip: 267, stem: 223, fault:467. flip_cnt: 37, stem_cnt: 94, fault_cnt:47 +[UP] flip: 98, stem: 449, fault:450. flip_cnt: 13, stem_cnt: 94, fault_cnt:49 +[UP] flip: 26, stem: 225, fault:525. flip_cnt: 3, stem_cnt: 95, fault_cnt:71 +[UP] flip: 26, stem: 225, fault:506. flip_cnt: 3, stem_cnt: 95, fault_cnt:65 +[UP] flip: 9, stem: 228, fault:507. flip_cnt: 1, stem_cnt: 95, fault_cnt:64 +[UP] flip: 56, stem: 1, fault:500. flip_cnt: 5, stem_cnt: 95, fault_cnt:64 +[UP] flip: 28, stem: 1, fault:487. flip_cnt: 3, stem_cnt: 95, fault_cnt:61 +[UP] flip: 103, stem: 3, fault:469. flip_cnt: 9, stem_cnt: 93, fault_cnt:60 +[UP] flip: 15, stem: 920, fault:717. flip_cnt: 1, stem_cnt: 92, fault_cnt:73 +[UP] flip: 522, stem: 920, fault:697. flip_cnt: 37, stem_cnt: 92, fault_cnt:74 +[UP] flip: 3, stem: 464, fault:782. flip_cnt: 1, stem_cnt: 94, fault_cnt:86 +[UP] flip: 62, stem: 223, fault:744. flip_cnt: 4, stem_cnt: 95, fault_cnt:76 +[UP] flip: 62, stem: 223, fault:744. flip_cnt: 4, stem_cnt: 95, fault_cnt:76 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:800. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 0.8699 pattern: 16 before: 54 now: 51 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1429, fault:225. flip_cnt: 0, stem_cnt: 89, fault_cnt:34 +[UP] flip: 68, stem: 957, fault:374. flip_cnt: 25, stem_cnt: 91, fault_cnt:55 +[UP] flip: 125, stem: 722, fault:339. flip_cnt: 37, stem_cnt: 91, fault_cnt:36 +[UP] flip: 19, stem: 482, fault:410. flip_cnt: 4, stem_cnt: 93, fault_cnt:46 +[UP] flip: 39, stem: 241, fault:406. flip_cnt: 7, stem_cnt: 94, fault_cnt:49 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:427. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 0.8699 pattern: 16 before: 51 now: 51 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 735, fault:269. flip_cnt: 9, stem_cnt: 90, fault_cnt:40 +[UP] flip: 7, stem: 989, fault:399. flip_cnt: 3, stem_cnt: 83, fault_cnt:57 +[UP] flip: 0, stem: 493, fault:534. flip_cnt: 0, stem_cnt: 93, fault_cnt:66 +[UP] flip: 10, stem: 742, fault:719. flip_cnt: 2, stem_cnt: 92, fault_cnt:75 +[UP] flip: 127, stem: 251, fault:573. flip_cnt: 28, stem_cnt: 92, fault_cnt:60 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:619. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 0.9107 pattern: 17 before: 51 now: 35 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1001, fault:215. flip_cnt: 0, stem_cnt: 91, fault_cnt:26 +[UP] flip: 0, stem: 1005, fault:295. flip_cnt: 0, stem_cnt: 91, fault_cnt:36 +[UP] flip: 22, stem: 253, fault:365. flip_cnt: 7, stem_cnt: 94, fault_cnt:43 +[UP] flip: 0, stem: 252, fault:450. flip_cnt: 0, stem_cnt: 95, fault_cnt:54 +[UP] flip: 6, stem: 1, fault:437. flip_cnt: 1, stem_cnt: 95, fault_cnt:44 +[UP] flip: 34, stem: 1, fault:419. flip_cnt: 7, stem_cnt: 95, fault_cnt:46 +[UP] flip: 24, stem: 2, fault:406. flip_cnt: 4, stem_cnt: 94, fault_cnt:45 +[UP] flip: 33, stem: 1, fault:500. flip_cnt: 7, stem_cnt: 95, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:538. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 0.9158 pattern: 18 before: 35 now: 33 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1037, fault:246. flip_cnt: 0, stem_cnt: 91, fault_cnt:36 +[UP] flip: 14, stem: 1309, fault:328. flip_cnt: 5, stem_cnt: 82, fault_cnt:48 +[UP] flip: 15, stem: 1565, fault:487. flip_cnt: 4, stem_cnt: 90, fault_cnt:55 +[UP] flip: 0, stem: 521, fault:572. flip_cnt: 0, stem_cnt: 94, fault_cnt:65 +[UP] flip: 26, stem: 3, fault:604. flip_cnt: 8, stem_cnt: 93, fault_cnt:69 +[UP] flip: 60, stem: 529, fault:763. flip_cnt: 11, stem_cnt: 93, fault_cnt:83 +[UP] flip: 13, stem: 529, fault:780. flip_cnt: 2, stem_cnt: 94, fault_cnt:85 +[UP] flip: 63, stem: 267, fault:780. flip_cnt: 8, stem_cnt: 94, fault_cnt:87 +[UP] flip: 56, stem: 262, fault:499. flip_cnt: 9, stem_cnt: 93, fault_cnt:61 +[UP] flip: 85, stem: 269, fault:462. flip_cnt: 10, stem_cnt: 94, fault_cnt:52 +[UP] flip: 10, stem: 536, fault:454. flip_cnt: 1, stem_cnt: 94, fault_cnt:45 +[UP] flip: 7, stem: 528, fault:548. flip_cnt: 1, stem_cnt: 94, fault_cnt:70 +[UP] flip: 265, stem: 536, fault:383. flip_cnt: 27, stem_cnt: 92, fault_cnt:57 +[UP] flip: 191, stem: 813, fault:283. flip_cnt: 16, stem_cnt: 93, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:383. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 0.9209 pattern: 19 before: 33 now: 31 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 1099, fault:188. flip_cnt: 9, stem_cnt: 89, fault_cnt:32 +[UP] flip: 8, stem: 825, fault:378. flip_cnt: 3, stem_cnt: 93, fault_cnt:58 +[UP] flip: 24, stem: 551, fault:352. flip_cnt: 9, stem_cnt: 93, fault_cnt:53 +[UP] flip: 13, stem: 1106, fault:330. flip_cnt: 3, stem_cnt: 87, fault_cnt:47 +[UP] flip: 16, stem: 1112, fault:362. flip_cnt: 3, stem_cnt: 92, fault_cnt:53 +[UP] flip: 49, stem: 837, fault:318. flip_cnt: 8, stem_cnt: 92, fault_cnt:43 +[UP] flip: 53, stem: 277, fault:467. flip_cnt: 15, stem_cnt: 95, fault_cnt:52 +[UP] flip: 43, stem: 1, fault:510. flip_cnt: 7, stem_cnt: 95, fault_cnt:55 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:530. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9209 pattern: 19 before: 31 now: 31 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1982, fault:251. flip_cnt: 0, stem_cnt: 88, fault_cnt:33 +[UP] flip: 12, stem: 3, fault:265. flip_cnt: 7, stem_cnt: 93, fault_cnt:34 +[UP] flip: 37, stem: 286, fault:374. flip_cnt: 15, stem_cnt: 94, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9209 pattern: 19 before: 31 now: 31 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 1149, fault:290. flip_cnt: 4, stem_cnt: 91, fault_cnt:49 +[UP] flip: 3, stem: 577, fault:648. flip_cnt: 1, stem_cnt: 93, fault_cnt:77 +[UP] flip: 60, stem: 289, fault:696. flip_cnt: 23, stem_cnt: 94, fault_cnt:81 +[UP] flip: 67, stem: 577, fault:616. flip_cnt: 19, stem_cnt: 94, fault_cnt:71 +[UP] flip: 57, stem: 290, fault:621. flip_cnt: 11, stem_cnt: 93, fault_cnt:70 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:660. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 0.9235 pattern: 20 before: 31 now: 30 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1466, fault:355. flip_cnt: 0, stem_cnt: 90, fault_cnt:37 +[UP] flip: 3, stem: 882, fault:470. flip_cnt: 1, stem_cnt: 93, fault_cnt:59 +[UP] flip: 13, stem: 1771, fault:650. flip_cnt: 4, stem_cnt: 89, fault_cnt:61 +[UP] flip: 10, stem: 886, fault:700. flip_cnt: 2, stem_cnt: 93, fault_cnt:85 +[UP] flip: 50, stem: 2660, fault:693. flip_cnt: 11, stem_cnt: 86, fault_cnt:82 +[UP] flip: 24, stem: 591, fault:686. flip_cnt: 4, stem_cnt: 94, fault_cnt:79 +[UP] flip: 252, stem: 890, fault:659. flip_cnt: 37, stem_cnt: 93, fault_cnt:79 +[UP] flip: 13, stem: 1186, fault:657. flip_cnt: 2, stem_cnt: 90, fault_cnt:105 +[UP] flip: 16, stem: 2087, fault:676. flip_cnt: 2, stem_cnt: 91, fault_cnt:104 +[UP] flip: 18, stem: 2391, fault:643. flip_cnt: 2, stem_cnt: 91, fault_cnt:97 +[UP] flip: 67, stem: 1491, fault:626. flip_cnt: 9, stem_cnt: 93, fault_cnt:103 +[UP] flip: 10, stem: 2363, fault:614. flip_cnt: 1, stem_cnt: 87, fault_cnt:102 +[UP] flip: 11, stem: 2363, fault:614. flip_cnt: 1, stem_cnt: 87, fault_cnt:102 +[UP] flip: 19, stem: 306, fault:656. flip_cnt: 2, stem_cnt: 95, fault_cnt:94 +[UP] flip: 149, stem: 602, fault:593. flip_cnt: 11, stem_cnt: 94, fault_cnt:87 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:597. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 0.9260 pattern: 21 before: 30 now: 29 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 1546, fault:338. flip_cnt: 2, stem_cnt: 90, fault_cnt:45 +[UP] flip: 5, stem: 1240, fault:582. flip_cnt: 2, stem_cnt: 92, fault_cnt:76 +[UP] flip: 6, stem: 934, fault:658. flip_cnt: 2, stem_cnt: 92, fault_cnt:77 +[UP] flip: 8, stem: 625, fault:663. flip_cnt: 2, stem_cnt: 93, fault_cnt:78 +[UP] flip: 0, stem: 1248, fault:680. flip_cnt: 0, stem_cnt: 93, fault_cnt:78 +[UP] flip: 0, stem: 937, fault:702. flip_cnt: 0, stem_cnt: 94, fault_cnt:79 +[UP] flip: 50, stem: 316, fault:462. flip_cnt: 7, stem_cnt: 94, fault_cnt:58 +[UP] flip: 0, stem: 1, fault:481. flip_cnt: 0, stem_cnt: 95, fault_cnt:59 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:481. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9286 pattern: 22 before: 29 now: 28 +checking valid circuit ... result: 1. +local search! +[UP] flip: 19, stem: 955, fault:231. flip_cnt: 11, stem_cnt: 92, fault_cnt:28 +[UP] flip: 0, stem: 1279, fault:492. flip_cnt: 0, stem_cnt: 89, fault_cnt:64 +[UP] flip: 7, stem: 1279, fault:594. flip_cnt: 2, stem_cnt: 92, fault_cnt:78 +[UP] flip: 8, stem: 1927, fault:607. flip_cnt: 2, stem_cnt: 89, fault_cnt:68 +[UP] flip: 24, stem: 967, fault:558. flip_cnt: 5, stem_cnt: 92, fault_cnt:64 +[UP] flip: 4, stem: 968, fault:618. flip_cnt: 1, stem_cnt: 93, fault_cnt:71 +[UP] flip: 0, stem: 963, fault:624. flip_cnt: 0, stem_cnt: 94, fault_cnt:79 +[UP] flip: 7, stem: 648, fault:631. flip_cnt: 1, stem_cnt: 94, fault_cnt:71 +[UP] flip: 17, stem: 648, fault:612. flip_cnt: 2, stem_cnt: 95, fault_cnt:70 +[UP] flip: 91, stem: 1, fault:673. flip_cnt: 11, stem_cnt: 95, fault_cnt:79 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:712. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 0.9286 pattern: 22 before: 28 now: 28 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 988, fault:195. flip_cnt: 0, stem_cnt: 92, fault_cnt:22 +[UP] flip: 29, stem: 1, fault:282. flip_cnt: 15, stem_cnt: 95, fault_cnt:32 +[UP] flip: 0, stem: 660, fault:398. flip_cnt: 0, stem_cnt: 94, fault_cnt:46 +[UP] flip: 11, stem: 997, fault:430. flip_cnt: 3, stem_cnt: 92, fault_cnt:48 +[UP] flip: 49, stem: 0, fault:493. flip_cnt: 12, stem_cnt: 96, fault_cnt:71 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:493. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 0.9439 pattern: 23 before: 28 now: 22 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 2011, fault:263. flip_cnt: 0, stem_cnt: 89, fault_cnt:32 +[UP] flip: 9, stem: 1346, fault:260. flip_cnt: 4, stem_cnt: 90, fault_cnt:31 +[UP] flip: 48, stem: 1686, fault:540. flip_cnt: 15, stem_cnt: 90, fault_cnt:67 +[UP] flip: 19, stem: 1689, fault:562. flip_cnt: 4, stem_cnt: 91, fault_cnt:60 +[UP] flip: 42, stem: 675, fault:658. flip_cnt: 9, stem_cnt: 94, fault_cnt:71 +[UP] flip: 12, stem: 338, fault:659. flip_cnt: 2, stem_cnt: 95, fault_cnt:74 +[UP] flip: 37, stem: 1, fault:599. flip_cnt: 5, stem_cnt: 95, fault_cnt:64 +[UP] flip: 32, stem: 342, fault:599. flip_cnt: 4, stem_cnt: 95, fault_cnt:62 +[UP] flip: 278, stem: 336, fault:493. flip_cnt: 31, stem_cnt: 95, fault_cnt:61 +[UP] flip: 89, stem: 672, fault:339. flip_cnt: 9, stem_cnt: 93, fault_cnt:45 +[UP] flip: 0, stem: 336, fault:358. flip_cnt: 0, stem_cnt: 95, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:358. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9439 pattern: 23 before: 22 now: 22 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 1737, fault:222. flip_cnt: 4, stem_cnt: 89, fault_cnt:18 +[UP] flip: 11, stem: 1741, fault:349. flip_cnt: 4, stem_cnt: 90, fault_cnt:38 +[UP] flip: 1, stem: 1396, fault:521. flip_cnt: 1, stem_cnt: 92, fault_cnt:56 +[UP] flip: 4, stem: 1745, fault:637. flip_cnt: 2, stem_cnt: 92, fault_cnt:66 +[UP] flip: 0, stem: 1049, fault:675. flip_cnt: 0, stem_cnt: 94, fault_cnt:72 +[UP] flip: 45, stem: 1, fault:675. flip_cnt: 8, stem_cnt: 95, fault_cnt:71 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:695. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 0.9439 pattern: 23 before: 22 now: 22 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 1772, fault:287. flip_cnt: 2, stem_cnt: 89, fault_cnt:62 +[UP] flip: 6, stem: 1066, fault:614. flip_cnt: 2, stem_cnt: 92, fault_cnt:76 +[UP] flip: 6, stem: 1423, fault:616. flip_cnt: 2, stem_cnt: 92, fault_cnt:78 +[UP] flip: 5, stem: 1072, fault:429. flip_cnt: 1, stem_cnt: 92, fault_cnt:60 +[UP] flip: 86, stem: 2501, fault:393. flip_cnt: 15, stem_cnt: 91, fault_cnt:58 +[UP] flip: 105, stem: 719, fault:421. flip_cnt: 16, stem_cnt: 93, fault_cnt:60 +[UP] flip: 0, stem: 0, fault:481. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:481. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 0.9464 pattern: 24 before: 22 now: 21 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 1089, fault:223. flip_cnt: 9, stem_cnt: 90, fault_cnt:35 +[UP] flip: 3, stem: 2, fault:277. flip_cnt: 1, stem_cnt: 94, fault_cnt:31 +[UP] flip: 14, stem: 728, fault:242. flip_cnt: 4, stem_cnt: 94, fault_cnt:33 +[UP] flip: 30, stem: 1826, fault:318. flip_cnt: 7, stem_cnt: 90, fault_cnt:39 +[UP] flip: 9, stem: 2928, fault:483. flip_cnt: 2, stem_cnt: 88, fault_cnt:75 +[UP] flip: 26, stem: 2566, fault:474. flip_cnt: 6, stem_cnt: 90, fault_cnt:71 +[UP] flip: 6, stem: 2196, fault:413. flip_cnt: 1, stem_cnt: 92, fault_cnt:68 +[UP] flip: 64, stem: 731, fault:465. flip_cnt: 10, stem_cnt: 94, fault_cnt:56 +[UP] flip: 53, stem: 1100, fault:465. flip_cnt: 8, stem_cnt: 94, fault_cnt:56 +[UP] flip: 74, stem: 372, fault:448. flip_cnt: 12, stem_cnt: 94, fault_cnt:56 +[UP] flip: 36, stem: 0, fault:488. flip_cnt: 5, stem_cnt: 96, fault_cnt:59 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:554. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 0.9592 pattern: 25 before: 21 now: 16 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 375, fault:167. flip_cnt: 0, stem_cnt: 94, fault_cnt:24 +[UP] flip: 0, stem: 751, fault:318. flip_cnt: 0, stem_cnt: 93, fault_cnt:47 +[UP] flip: 29, stem: 1128, fault:412. flip_cnt: 9, stem_cnt: 92, fault_cnt:65 +[UP] flip: 4, stem: 3016, fault:446. flip_cnt: 2, stem_cnt: 88, fault_cnt:80 +[UP] flip: 0, stem: 2265, fault:426. flip_cnt: 0, stem_cnt: 91, fault_cnt:75 +[UP] flip: 130, stem: 381, fault:350. flip_cnt: 28, stem_cnt: 93, fault_cnt:58 +[UP] flip: 0, stem: 0, fault:381. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:381. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 0.9643 pattern: 26 before: 16 now: 14 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1529, fault:164. flip_cnt: 0, stem_cnt: 91, fault_cnt:20 +[UP] flip: 23, stem: 767, fault:354. flip_cnt: 10, stem_cnt: 93, fault_cnt:39 +[UP] flip: 29, stem: 385, fault:378. flip_cnt: 10, stem_cnt: 94, fault_cnt:44 +[UP] flip: 32, stem: 769, fault:401. flip_cnt: 9, stem_cnt: 94, fault_cnt:53 +[UP] flip: 91, stem: 770, fault:343. flip_cnt: 20, stem_cnt: 93, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:332. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9643 pattern: 26 before: 14 now: 14 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 2329, fault:185. flip_cnt: 0, stem_cnt: 89, fault_cnt:30 +[UP] flip: 0, stem: 779, fault:229. flip_cnt: 0, stem_cnt: 93, fault_cnt:38 +[UP] flip: 9, stem: 391, fault:386. flip_cnt: 3, stem_cnt: 94, fault_cnt:53 +[UP] flip: 31, stem: 782, fault:345. flip_cnt: 7, stem_cnt: 93, fault_cnt:41 +[UP] flip: 33, stem: 1169, fault:400. flip_cnt: 9, stem_cnt: 93, fault_cnt:54 +[UP] flip: 15, stem: 781, fault:385. flip_cnt: 3, stem_cnt: 94, fault_cnt:46 +[UP] flip: 52, stem: 1, fault:367. flip_cnt: 10, stem_cnt: 95, fault_cnt:40 +[UP] flip: 51, stem: 2, fault:365. flip_cnt: 7, stem_cnt: 94, fault_cnt:43 +[UP] flip: 116, stem: 2, fault:355. flip_cnt: 15, stem_cnt: 94, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:404. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 0.9643 pattern: 26 before: 14 now: 14 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3185, fault:194. flip_cnt: 0, stem_cnt: 87, fault_cnt:30 +[UP] flip: 0, stem: 2393, fault:346. flip_cnt: 0, stem_cnt: 90, fault_cnt:50 +[UP] flip: 13, stem: 1601, fault:546. flip_cnt: 5, stem_cnt: 91, fault_cnt:71 +[UP] flip: 4, stem: 1603, fault:568. flip_cnt: 1, stem_cnt: 92, fault_cnt:68 +[UP] flip: 10, stem: 2011, fault:570. flip_cnt: 2, stem_cnt: 90, fault_cnt:91 +[UP] flip: 0, stem: 1206, fault:570. flip_cnt: 0, stem_cnt: 94, fault_cnt:97 +[UP] flip: 14, stem: 398, fault:581. flip_cnt: 2, stem_cnt: 95, fault_cnt:98 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:560. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 0.9643 pattern: 26 before: 14 now: 14 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 2030, fault:257. flip_cnt: 7, stem_cnt: 91, fault_cnt:76 +[UP] flip: 18, stem: 1221, fault:357. flip_cnt: 9, stem_cnt: 92, fault_cnt:81 +[UP] flip: 27, stem: 1629, fault:471. flip_cnt: 9, stem_cnt: 91, fault_cnt:103 +[UP] flip: 0, stem: 410, fault:433. flip_cnt: 0, stem_cnt: 94, fault_cnt:50 +[UP] flip: 162, stem: 819, fault:365. flip_cnt: 37, stem_cnt: 93, fault_cnt:44 +[UP] flip: 15, stem: 1644, fault:500. flip_cnt: 3, stem_cnt: 92, fault_cnt:70 +[UP] flip: 36, stem: 406, fault:452. flip_cnt: 5, stem_cnt: 95, fault_cnt:65 +[UP] flip: 19, stem: 406, fault:436. flip_cnt: 3, stem_cnt: 95, fault_cnt:62 +[UP] flip: 42, stem: 406, fault:452. flip_cnt: 5, stem_cnt: 95, fault_cnt:66 +[UP] flip: 18, stem: 406, fault:436. flip_cnt: 3, stem_cnt: 95, fault_cnt:62 +[UP] flip: 34, stem: 406, fault:453. flip_cnt: 5, stem_cnt: 95, fault_cnt:66 +[UP] flip: 80, stem: 1230, fault:436. flip_cnt: 9, stem_cnt: 92, fault_cnt:65 +[UP] flip: 300, stem: 2079, fault:531. flip_cnt: 27, stem_cnt: 90, fault_cnt:72 +[UP] flip: 0, stem: 1658, fault:535. flip_cnt: 0, stem_cnt: 93, fault_cnt:61 +[UP] flip: 8, stem: 838, fault:516. flip_cnt: 1, stem_cnt: 94, fault_cnt:53 +[UP] flip: 27, stem: 414, fault:500. flip_cnt: 2, stem_cnt: 95, fault_cnt:57 +[UP] flip: 15, stem: 414, fault:500. flip_cnt: 1, stem_cnt: 95, fault_cnt:57 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:500. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9643 pattern: 26 before: 14 now: 14 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 1272, fault:169. flip_cnt: 7, stem_cnt: 93, fault_cnt:49 +[UP] flip: 6, stem: 1700, fault:319. flip_cnt: 2, stem_cnt: 92, fault_cnt:82 +[UP] flip: 25, stem: 2981, fault:300. flip_cnt: 9, stem_cnt: 88, fault_cnt:46 +[UP] flip: 74, stem: 2, fault:365. flip_cnt: 19, stem_cnt: 94, fault_cnt:45 +[UP] flip: 0, stem: 857, fault:377. flip_cnt: 0, stem_cnt: 93, fault_cnt:50 +[UP] flip: 42, stem: 856, fault:377. flip_cnt: 7, stem_cnt: 95, fault_cnt:50 +[UP] flip: 63, stem: 1, fault:400. flip_cnt: 10, stem_cnt: 95, fault_cnt:47 +[UP] flip: 62, stem: 1, fault:400. flip_cnt: 10, stem_cnt: 95, fault_cnt:47 +[UP] flip: 64, stem: 1, fault:400. flip_cnt: 10, stem_cnt: 95, fault_cnt:47 +[UP] flip: 225, stem: 429, fault:310. flip_cnt: 27, stem_cnt: 92, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:290. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 0.9643 pattern: 26 before: 14 now: 14 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 1742, fault:283. flip_cnt: 9, stem_cnt: 90, fault_cnt:51 +[UP] flip: 5, stem: 2181, fault:512. flip_cnt: 2, stem_cnt: 90, fault_cnt:64 +[UP] flip: 5, stem: 1747, fault:542. flip_cnt: 2, stem_cnt: 92, fault_cnt:69 +[UP] flip: 8, stem: 439, fault:607. flip_cnt: 2, stem_cnt: 94, fault_cnt:78 +[UP] flip: 22, stem: 440, fault:577. flip_cnt: 4, stem_cnt: 94, fault_cnt:66 +[UP] flip: 13, stem: 441, fault:406. flip_cnt: 3, stem_cnt: 94, fault_cnt:52 +[UP] flip: 54, stem: 1313, fault:388. flip_cnt: 9, stem_cnt: 92, fault_cnt:51 +[UP] flip: 75, stem: 1, fault:385. flip_cnt: 10, stem_cnt: 95, fault_cnt:42 +[UP] flip: 307, stem: 436, fault:381. flip_cnt: 37, stem_cnt: 94, fault_cnt:45 +[UP] flip: 28, stem: 888, fault:454. flip_cnt: 3, stem_cnt: 94, fault_cnt:64 +[UP] flip: 25, stem: 438, fault:439. flip_cnt: 3, stem_cnt: 95, fault_cnt:63 +[UP] flip: 30, stem: 439, fault:423. flip_cnt: 3, stem_cnt: 95, fault_cnt:57 +[UP] flip: 58, stem: 439, fault:420. flip_cnt: 5, stem_cnt: 95, fault_cnt:56 +[UP] flip: 61, stem: 439, fault:420. flip_cnt: 5, stem_cnt: 95, fault_cnt:57 +[UP] flip: 68, stem: 439, fault:450. flip_cnt: 5, stem_cnt: 95, fault_cnt:58 +[UP] flip: 63, stem: 439, fault:431. flip_cnt: 5, stem_cnt: 95, fault_cnt:59 +[UP] flip: 41, stem: 451, fault:470. flip_cnt: 3, stem_cnt: 95, fault_cnt:63 +[UP] flip: 65, stem: 3596, fault:431. flip_cnt: 5, stem_cnt: 95, fault_cnt:59 +[UP] flip: 41, stem: 453, fault:487. flip_cnt: 3, stem_cnt: 95, fault_cnt:67 +[UP] flip: 47, stem: 1, fault:471. flip_cnt: 3, stem_cnt: 95, fault_cnt:65 +[UP] flip: 48, stem: 1, fault:434. flip_cnt: 3, stem_cnt: 95, fault_cnt:59 +[UP] flip: 83, stem: 3141, fault:431. flip_cnt: 5, stem_cnt: 95, fault_cnt:58 +[UP] flip: 90, stem: 2685, fault:431. flip_cnt: 5, stem_cnt: 95, fault_cnt:59 +[UP] flip: 89, stem: 2228, fault:431. flip_cnt: 5, stem_cnt: 95, fault_cnt:59 +[UP] flip: 90, stem: 1770, fault:431. flip_cnt: 5, stem_cnt: 95, fault_cnt:59 +[UP] flip: 20, stem: 1782, fault:701. flip_cnt: 1, stem_cnt: 93, fault_cnt:88 +[UP] flip: 0, stem: 2276, fault:691. flip_cnt: 0, stem_cnt: 93, fault_cnt:89 +[UP] flip: 52, stem: 879, fault:710. flip_cnt: 2, stem_cnt: 94, fault_cnt:108 +[UP] flip: 163, stem: 872, fault:674. flip_cnt: 9, stem_cnt: 93, fault_cnt:104 +[UP] flip: 20, stem: 3923, fault:681. flip_cnt: 1, stem_cnt: 89, fault_cnt:103 +[UP] flip: 50, stem: 4981, fault:681. flip_cnt: 2, stem_cnt: 90, fault_cnt:99 +[UP] flip: 20, stem: 4857, fault:603. flip_cnt: 1, stem_cnt: 86, fault_cnt:92 +[UP] flip: 351, stem: 4000, fault:571. flip_cnt: 13, stem_cnt: 93, fault_cnt:89 +[UP] flip: 30, stem: 1621, fault:591. flip_cnt: 1, stem_cnt: 94, fault_cnt:59 +[UP] flip: 23, stem: 1212, fault:572. flip_cnt: 1, stem_cnt: 94, fault_cnt:79 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:591. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 0.9643 pattern: 26 before: 14 now: 14 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 2356, fault:228. flip_cnt: 7, stem_cnt: 90, fault_cnt:28 +[UP] flip: 11, stem: 1418, fault:247. flip_cnt: 4, stem_cnt: 91, fault_cnt:32 +[UP] flip: 0, stem: 1420, fault:375. flip_cnt: 0, stem_cnt: 92, fault_cnt:48 +[UP] flip: 31, stem: 1421, fault:338. flip_cnt: 7, stem_cnt: 92, fault_cnt:52 +[UP] flip: 11, stem: 1904, fault:376. flip_cnt: 3, stem_cnt: 85, fault_cnt:57 +[UP] flip: 0, stem: 953, fault:433. flip_cnt: 0, stem_cnt: 93, fault_cnt:80 +[UP] flip: 26, stem: 952, fault:394. flip_cnt: 4, stem_cnt: 95, fault_cnt:72 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:458. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9643 pattern: 26 before: 14 now: 14 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 482, fault:131. flip_cnt: 9, stem_cnt: 92, fault_cnt:19 +[UP] flip: 0, stem: 961, fault:268. flip_cnt: 0, stem_cnt: 93, fault_cnt:36 +[UP] flip: 3, stem: 482, fault:383. flip_cnt: 1, stem_cnt: 94, fault_cnt:52 +[UP] flip: 13, stem: 1, fault:397. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 0, stem: 1450, fault:416. flip_cnt: 0, stem_cnt: 92, fault_cnt:58 +[UP] flip: 46, stem: 2, fault:351. flip_cnt: 7, stem_cnt: 94, fault_cnt:43 +[UP] flip: 61, stem: 1, fault:388. flip_cnt: 10, stem_cnt: 95, fault_cnt:48 +[UP] flip: 11, stem: 483, fault:412. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 40, stem: 480, fault:355. flip_cnt: 7, stem_cnt: 94, fault_cnt:46 +[UP] flip: 321, stem: 970, fault:336. flip_cnt: 37, stem_cnt: 93, fault_cnt:41 +[UP] flip: 43, stem: 479, fault:435. flip_cnt: 5, stem_cnt: 95, fault_cnt:64 +[UP] flip: 43, stem: 479, fault:454. flip_cnt: 5, stem_cnt: 95, fault_cnt:64 +[UP] flip: 61, stem: 479, fault:435. flip_cnt: 5, stem_cnt: 95, fault_cnt:64 +[UP] flip: 57, stem: 479, fault:435. flip_cnt: 5, stem_cnt: 95, fault_cnt:64 +[UP] flip: 34, stem: 479, fault:416. flip_cnt: 3, stem_cnt: 95, fault_cnt:61 +[UP] flip: 60, stem: 479, fault:435. flip_cnt: 5, stem_cnt: 95, fault_cnt:65 +[UP] flip: 136, stem: 977, fault:435. flip_cnt: 9, stem_cnt: 92, fault_cnt:64 +[UP] flip: 13, stem: 1480, fault:653. flip_cnt: 1, stem_cnt: 93, fault_cnt:81 +[UP] flip: 0, stem: 1482, fault:653. flip_cnt: 0, stem_cnt: 93, fault_cnt:81 +[UP] flip: 180, stem: 499, fault:664. flip_cnt: 11, stem_cnt: 94, fault_cnt:86 +[UP] flip: 0, stem: 1, fault:703. flip_cnt: 0, stem_cnt: 95, fault_cnt:86 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:703. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 0.9643 pattern: 26 before: 14 now: 14 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 2508, fault:286. flip_cnt: 9, stem_cnt: 88, fault_cnt:52 +[UP] flip: 8, stem: 4016, fault:439. flip_cnt: 3, stem_cnt: 88, fault_cnt:79 +[UP] flip: 20, stem: 3017, fault:539. flip_cnt: 9, stem_cnt: 89, fault_cnt:85 +[UP] flip: 28, stem: 3021, fault:478. flip_cnt: 7, stem_cnt: 85, fault_cnt:61 +[UP] flip: 9, stem: 3029, fault:498. flip_cnt: 2, stem_cnt: 90, fault_cnt:54 +[UP] flip: 71, stem: 2022, fault:481. flip_cnt: 13, stem_cnt: 92, fault_cnt:56 +[UP] flip: 0, stem: 1012, fault:578. flip_cnt: 0, stem_cnt: 94, fault_cnt:71 +[UP] flip: 12, stem: 1, fault:560. flip_cnt: 2, stem_cnt: 95, fault_cnt:66 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:560. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 0.9643 pattern: 26 before: 14 now: 14 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1531, fault:247. flip_cnt: 0, stem_cnt: 92, fault_cnt:70 +[UP] flip: 8, stem: 1024, fault:474. flip_cnt: 3, stem_cnt: 92, fault_cnt:61 +[UP] flip: 7, stem: 2047, fault:491. flip_cnt: 2, stem_cnt: 91, fault_cnt:61 +[UP] flip: 20, stem: 3075, fault:508. flip_cnt: 9, stem_cnt: 89, fault_cnt:68 +[UP] flip: 10, stem: 2049, fault:545. flip_cnt: 2, stem_cnt: 93, fault_cnt:77 +[UP] flip: 11, stem: 2060, fault:587. flip_cnt: 2, stem_cnt: 92, fault_cnt:76 +[UP] flip: 27, stem: 3084, fault:568. flip_cnt: 4, stem_cnt: 92, fault_cnt:67 +[UP] flip: 84, stem: 1535, fault:529. flip_cnt: 11, stem_cnt: 94, fault_cnt:77 +[UP] flip: 49, stem: 1018, fault:504. flip_cnt: 9, stem_cnt: 93, fault_cnt:70 +[UP] flip: 19, stem: 1541, fault:488. flip_cnt: 2, stem_cnt: 94, fault_cnt:66 +[UP] flip: 21, stem: 2059, fault:506. flip_cnt: 2, stem_cnt: 94, fault_cnt:68 +[UP] flip: 88, stem: 3086, fault:511. flip_cnt: 9, stem_cnt: 88, fault_cnt:66 +[UP] flip: 19, stem: 2611, fault:533. flip_cnt: 2, stem_cnt: 90, fault_cnt:64 +[UP] flip: 314, stem: 1047, fault:397. flip_cnt: 24, stem_cnt: 93, fault_cnt:59 +[UP] flip: 89, stem: 4185, fault:260. flip_cnt: 7, stem_cnt: 95, fault_cnt:28 +[UP] flip: 15, stem: 2075, fault:374. flip_cnt: 1, stem_cnt: 93, fault_cnt:40 +[UP] flip: 102, stem: 1541, fault:298. flip_cnt: 7, stem_cnt: 94, fault_cnt:37 +[UP] flip: 107, stem: 8327, fault:304. flip_cnt: 7, stem_cnt: 92, fault_cnt:34 +[UP] flip: 0, stem: 515, fault:474. flip_cnt: 0, stem_cnt: 95, fault_cnt:53 +[UP] flip: 73, stem: 0, fault:436. flip_cnt: 4, stem_cnt: 96, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 0.9643 pattern: 26 before: 14 now: 14 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 1596, fault:172. flip_cnt: 9, stem_cnt: 90, fault_cnt:28 +[UP] flip: 12, stem: 533, fault:312. flip_cnt: 5, stem_cnt: 94, fault_cnt:50 +[UP] flip: 10, stem: 3731, fault:387. flip_cnt: 3, stem_cnt: 89, fault_cnt:56 +[UP] flip: 43, stem: 3734, fault:346. flip_cnt: 9, stem_cnt: 89, fault_cnt:54 +[UP] flip: 0, stem: 2135, fault:378. flip_cnt: 0, stem_cnt: 93, fault_cnt:56 +[UP] flip: 89, stem: 1, fault:283. flip_cnt: 16, stem_cnt: 95, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:347. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 0.9643 pattern: 26 before: 14 now: 14 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1, fault:164. flip_cnt: 0, stem_cnt: 95, fault_cnt:24 +[UP] flip: 12, stem: 0, fault:212. flip_cnt: 4, stem_cnt: 96, fault_cnt:30 +[UP] flip: 0, stem: 1081, fault:362. flip_cnt: 0, stem_cnt: 93, fault_cnt:52 +[UP] flip: 0, stem: 542, fault:415. flip_cnt: 0, stem_cnt: 94, fault_cnt:76 +[UP] flip: 0, stem: 1, fault:415. flip_cnt: 0, stem_cnt: 95, fault_cnt:74 +[UP] flip: 8, stem: 0, fault:433. flip_cnt: 2, stem_cnt: 96, fault_cnt:75 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:484. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 0.9643 pattern: 26 before: 14 now: 14 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 546, fault:287. flip_cnt: 2, stem_cnt: 94, fault_cnt:59 +[UP] flip: 7, stem: 1638, fault:419. flip_cnt: 3, stem_cnt: 93, fault_cnt:74 +[UP] flip: 16, stem: 2188, fault:481. flip_cnt: 5, stem_cnt: 92, fault_cnt:78 +[UP] flip: 31, stem: 1646, fault:570. flip_cnt: 7, stem_cnt: 91, fault_cnt:76 +[UP] flip: 73, stem: 3295, fault:547. flip_cnt: 15, stem_cnt: 89, fault_cnt:62 +[UP] flip: 0, stem: 1099, fault:551. flip_cnt: 0, stem_cnt: 94, fault_cnt:62 +[UP] flip: 19, stem: 1098, fault:548. flip_cnt: 3, stem_cnt: 94, fault_cnt:68 +[UP] flip: 12, stem: 1, fault:647. flip_cnt: 2, stem_cnt: 95, fault_cnt:85 +[UP] flip: 17, stem: 1, fault:636. flip_cnt: 2, stem_cnt: 95, fault_cnt:84 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:636. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 0.9643 pattern: 26 before: 14 now: 14 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 2221, fault:353. flip_cnt: 6, stem_cnt: 91, fault_cnt:91 +[UP] flip: 21, stem: 1668, fault:440. flip_cnt: 9, stem_cnt: 92, fault_cnt:105 +[UP] flip: 12, stem: 2230, fault:285. flip_cnt: 4, stem_cnt: 90, fault_cnt:34 +[UP] flip: 38, stem: 2231, fault:311. flip_cnt: 11, stem_cnt: 92, fault_cnt:37 +[UP] flip: 55, stem: 2232, fault:327. flip_cnt: 12, stem_cnt: 93, fault_cnt:44 +[UP] flip: 21, stem: 1116, fault:422. flip_cnt: 5, stem_cnt: 94, fault_cnt:65 +[UP] flip: 17, stem: 556, fault:404. flip_cnt: 3, stem_cnt: 95, fault_cnt:62 +[UP] flip: 34, stem: 556, fault:423. flip_cnt: 5, stem_cnt: 95, fault_cnt:66 +[UP] flip: 26, stem: 1119, fault:433. flip_cnt: 3, stem_cnt: 94, fault_cnt:66 +[UP] flip: 24, stem: 1120, fault:433. flip_cnt: 4, stem_cnt: 94, fault_cnt:68 +[UP] flip: 75, stem: 1112, fault:415. flip_cnt: 9, stem_cnt: 93, fault_cnt:66 +[UP] flip: 0, stem: 3385, fault:542. flip_cnt: 0, stem_cnt: 90, fault_cnt:71 +[UP] flip: 0, stem: 3952, fault:525. flip_cnt: 0, stem_cnt: 91, fault_cnt:57 +[UP] flip: 48, stem: 1124, fault:555. flip_cnt: 4, stem_cnt: 94, fault_cnt:62 +[UP] flip: 16, stem: 1, fault:612. flip_cnt: 2, stem_cnt: 95, fault_cnt:75 +[UP] flip: 35, stem: 6235, fault:555. flip_cnt: 4, stem_cnt: 95, fault_cnt:63 +[UP] flip: 58, stem: 557, fault:575. flip_cnt: 4, stem_cnt: 95, fault_cnt:68 +[UP] flip: 53, stem: 5664, fault:537. flip_cnt: 4, stem_cnt: 95, fault_cnt:60 +[UP] flip: 6, stem: 1701, fault:594. flip_cnt: 1, stem_cnt: 94, fault_cnt:93 +[UP] flip: 27, stem: 1130, fault:575. flip_cnt: 2, stem_cnt: 95, fault_cnt:88 +[UP] flip: 34, stem: 556, fault:575. flip_cnt: 2, stem_cnt: 94, fault_cnt:87 +[UP] flip: 37, stem: 556, fault:575. flip_cnt: 2, stem_cnt: 94, fault_cnt:86 +[UP] flip: 139, stem: 1112, fault:556. flip_cnt: 9, stem_cnt: 93, fault_cnt:83 +[UP] flip: 19, stem: 5647, fault:551. flip_cnt: 1, stem_cnt: 92, fault_cnt:86 +[UP] flip: 20, stem: 5671, fault:553. flip_cnt: 1, stem_cnt: 84, fault_cnt:84 +[UP] flip: 0, stem: 3934, fault:496. flip_cnt: 0, stem_cnt: 87, fault_cnt:81 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:592. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 0.9847 pattern: 27 before: 14 now: 6 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 2329, fault:109. flip_cnt: 0, stem_cnt: 91, fault_cnt:17 +[UP] flip: 7, stem: 2335, fault:169. flip_cnt: 3, stem_cnt: 89, fault_cnt:32 +[UP] flip: 23, stem: 1169, fault:294. flip_cnt: 8, stem_cnt: 93, fault_cnt:47 +[UP] flip: 41, stem: 582, fault:298. flip_cnt: 10, stem_cnt: 95, fault_cnt:41 +[UP] flip: 67, stem: 2, fault:271. flip_cnt: 15, stem_cnt: 94, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:289. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9847 pattern: 27 before: 6 now: 6 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 2353, fault:115. flip_cnt: 7, stem_cnt: 91, fault_cnt:28 +[UP] flip: 0, stem: 1179, fault:174. flip_cnt: 0, stem_cnt: 93, fault_cnt:37 +[UP] flip: 18, stem: 1771, fault:321. flip_cnt: 5, stem_cnt: 92, fault_cnt:63 +[UP] flip: 13, stem: 1, fault:307. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 46, stem: 590, fault:287. flip_cnt: 9, stem_cnt: 93, fault_cnt:49 +[UP] flip: 217, stem: 1184, fault:285. flip_cnt: 37, stem_cnt: 93, fault_cnt:54 +[UP] flip: 11, stem: 2965, fault:299. flip_cnt: 2, stem_cnt: 91, fault_cnt:57 +[UP] flip: 77, stem: 596, fault:273. flip_cnt: 12, stem_cnt: 94, fault_cnt:54 +[UP] flip: 14, stem: 1192, fault:319. flip_cnt: 2, stem_cnt: 93, fault_cnt:58 +[UP] flip: 33, stem: 593, fault:319. flip_cnt: 4, stem_cnt: 95, fault_cnt:49 +[UP] flip: 252, stem: 1191, fault:231. flip_cnt: 27, stem_cnt: 92, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9847 pattern: 27 before: 6 now: 6 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 1209, fault:138. flip_cnt: 3, stem_cnt: 85, fault_cnt:47 +[UP] flip: 21, stem: 5410, fault:194. flip_cnt: 9, stem_cnt: 85, fault_cnt:46 +[UP] flip: 11, stem: 1806, fault:204. flip_cnt: 3, stem_cnt: 93, fault_cnt:54 +[UP] flip: 0, stem: 1204, fault:272. flip_cnt: 0, stem_cnt: 94, fault_cnt:44 +[UP] flip: 106, stem: 1206, fault:264. flip_cnt: 27, stem_cnt: 93, fault_cnt:42 +[UP] flip: 6, stem: 1, fault:260. flip_cnt: 1, stem_cnt: 95, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:279. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9898 pattern: 28 before: 6 now: 4 +checking valid circuit ... result: 1. +local search! +[UP] flip: 11, stem: 3037, fault:86. flip_cnt: 9, stem_cnt: 89, fault_cnt:20 +[UP] flip: 8, stem: 1217, fault:148. flip_cnt: 4, stem_cnt: 93, fault_cnt:60 +[UP] flip: 0, stem: 2436, fault:264. flip_cnt: 0, stem_cnt: 92, fault_cnt:34 +[UP] flip: 0, stem: 611, fault:279. flip_cnt: 0, stem_cnt: 94, fault_cnt:53 +[UP] flip: 33, stem: 607, fault:284. flip_cnt: 7, stem_cnt: 95, fault_cnt:44 +[UP] flip: 14, stem: 1, fault:284. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 41, stem: 608, fault:284. flip_cnt: 7, stem_cnt: 94, fault_cnt:40 +[UP] flip: 83, stem: 2, fault:232. flip_cnt: 11, stem_cnt: 94, fault_cnt:44 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:251. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 0.9898 pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3697, fault:82. flip_cnt: 0, stem_cnt: 89, fault_cnt:14 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:243. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9898 pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 4945, fault:86. flip_cnt: 0, stem_cnt: 87, fault_cnt:53 +[UP] flip: 17, stem: 620, fault:115. flip_cnt: 6, stem_cnt: 94, fault_cnt:46 +[UP] flip: 25, stem: 1237, fault:130. flip_cnt: 9, stem_cnt: 93, fault_cnt:80 +[UP] flip: 3, stem: 620, fault:134. flip_cnt: 1, stem_cnt: 93, fault_cnt:58 +[UP] flip: 0, stem: 1, fault:139. flip_cnt: 0, stem_cnt: 95, fault_cnt:67 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:139. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 0.9898 pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +local search! +[UP] flip: 45, stem: 2497, fault:142. flip_cnt: 23, stem_cnt: 91, fault_cnt:74 +[UP] flip: 12, stem: 626, fault:226. flip_cnt: 4, stem_cnt: 94, fault_cnt:47 +[UP] flip: 0, stem: 1253, fault:244. flip_cnt: 0, stem_cnt: 93, fault_cnt:51 +[UP] flip: 11, stem: 1880, fault:247. flip_cnt: 3, stem_cnt: 93, fault_cnt:51 +[UP] flip: 55, stem: 1258, fault:238. flip_cnt: 11, stem_cnt: 92, fault_cnt:43 +[UP] flip: 89, stem: 1887, fault:206. flip_cnt: 15, stem_cnt: 92, fault_cnt:44 +[UP] flip: 11, stem: 2514, fault:226. flip_cnt: 2, stem_cnt: 94, fault_cnt:40 +[UP] flip: 25, stem: 1257, fault:244. flip_cnt: 3, stem_cnt: 94, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:244. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9898 pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 5064, fault:89. flip_cnt: 7, stem_cnt: 88, fault_cnt:54 +[UP] flip: 12, stem: 635, fault:115. flip_cnt: 4, stem_cnt: 94, fault_cnt:34 +[UP] flip: 42, stem: 1, fault:132. flip_cnt: 11, stem_cnt: 95, fault_cnt:41 +[UP] flip: 32, stem: 637, fault:237. flip_cnt: 11, stem_cnt: 94, fault_cnt:63 +[UP] flip: 0, stem: 1, fault:278. flip_cnt: 0, stem_cnt: 95, fault_cnt:70 +[UP] flip: 0, stem: 1, fault:278. flip_cnt: 0, stem_cnt: 95, fault_cnt:68 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:278. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 0.9898 pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 1923, fault:88. flip_cnt: 9, stem_cnt: 90, fault_cnt:16 +[UP] flip: 1, stem: 1284, fault:134. flip_cnt: 1, stem_cnt: 92, fault_cnt:18 +[UP] flip: 25, stem: 3209, fault:153. flip_cnt: 7, stem_cnt: 91, fault_cnt:28 +[UP] flip: 0, stem: 3209, fault:157. flip_cnt: 0, stem_cnt: 93, fault_cnt:40 +[UP] flip: 15, stem: 2, fault:142. flip_cnt: 4, stem_cnt: 94, fault_cnt:24 +[UP] flip: 51, stem: 1, fault:218. flip_cnt: 11, stem_cnt: 95, fault_cnt:22 +[UP] flip: 12, stem: 1, fault:199. flip_cnt: 2, stem_cnt: 95, fault_cnt:28 +[UP] flip: 49, stem: 0, fault:237. flip_cnt: 7, stem_cnt: 96, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:237. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 0.9898 pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 1956, fault:88. flip_cnt: 3, stem_cnt: 84, fault_cnt:50 +[UP] flip: 0, stem: 1301, fault:197. flip_cnt: 0, stem_cnt: 93, fault_cnt:50 +[UP] flip: 12, stem: 1954, fault:165. flip_cnt: 3, stem_cnt: 92, fault_cnt:20 +[UP] flip: 168, stem: 1956, fault:200. flip_cnt: 37, stem_cnt: 92, fault_cnt:29 +[UP] flip: 8, stem: 3910, fault:201. flip_cnt: 2, stem_cnt: 90, fault_cnt:47 +[UP] flip: 0, stem: 1959, fault:223. flip_cnt: 0, stem_cnt: 94, fault_cnt:50 +[UP] flip: 17, stem: 1307, fault:223. flip_cnt: 3, stem_cnt: 94, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:223. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 0.9923 pattern: 29 before: 4 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 3942, fault:3. flip_cnt: 4, stem_cnt: 90, fault_cnt:68 +[UP] flip: 14, stem: 2639, fault:9. flip_cnt: 7, stem_cnt: 84, fault_cnt:68 +[UP] flip: 14, stem: 2638, fault:20. flip_cnt: 4, stem_cnt: 90, fault_cnt:58 +[UP] flip: 132, stem: 2, fault:20. flip_cnt: 37, stem_cnt: 94, fault_cnt:65 +[UP] flip: 0, stem: 2, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:67 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 3316, fault:3. flip_cnt: 4, stem_cnt: 90, fault_cnt:46 +[UP] flip: 20, stem: 1993, fault:9. flip_cnt: 7, stem_cnt: 92, fault_cnt:33 +[UP] flip: 0, stem: 666, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:44 +[UP] flip: 0, stem: 667, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:51 +[UP] flip: 35, stem: 1333, fault:19. flip_cnt: 9, stem_cnt: 94, fault_cnt:51 +[UP] flip: 40, stem: 1, fault:19. flip_cnt: 7, stem_cnt: 95, fault_cnt:32 +[UP] flip: 197, stem: 664, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:29 +[UP] flip: 5, stem: 666, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:32 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 2017, fault:3. flip_cnt: 4, stem_cnt: 92, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 3373, fault:3. flip_cnt: 9, stem_cnt: 88, fault_cnt:68 +[UP] flip: 25, stem: 2701, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:42 +[UP] flip: 0, stem: 682, fault:20. flip_cnt: 0, stem_cnt: 87, fault_cnt:41 +[UP] flip: 16, stem: 2709, fault:20. flip_cnt: 4, stem_cnt: 91, fault_cnt:42 +[UP] flip: 34, stem: 679, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 11, stem: 3401, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:24 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 685, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:31 +[UP] flip: 7, stem: 1365, fault:9. flip_cnt: 3, stem_cnt: 94, fault_cnt:36 +[UP] flip: 16, stem: 2053, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:29 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 687, fault:3. flip_cnt: 11, stem_cnt: 94, fault_cnt:31 +[UP] flip: 3, stem: 1, fault:9. flip_cnt: 1, stem_cnt: 95, fault_cnt:35 +[UP] flip: 73, stem: 689, fault:20. flip_cnt: 23, stem_cnt: 94, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 2073, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:39 +[UP] flip: 6, stem: 1384, fault:9. flip_cnt: 2, stem_cnt: 92, fault_cnt:43 +[UP] flip: 9, stem: 2769, fault:20. flip_cnt: 3, stem_cnt: 91, fault_cnt:56 +[UP] flip: 0, stem: 2768, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:53 +[UP] flip: 0, stem: 3464, fault:20. flip_cnt: 0, stem_cnt: 87, fault_cnt:50 +[UP] flip: 0, stem: 2773, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:54 +[UP] flip: 0, stem: 2083, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:52 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 3492, fault:3. flip_cnt: 7, stem_cnt: 89, fault_cnt:21 +[UP] flip: 0, stem: 700, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:52 +[UP] flip: 0, stem: 700, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 3512, fault:3. flip_cnt: 7, stem_cnt: 89, fault_cnt:21 +[UP] flip: 94, stem: 3517, fault:9. flip_cnt: 37, stem_cnt: 89, fault_cnt:31 +[UP] flip: 3, stem: 2111, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:54 +[UP] flip: 90, stem: 2816, fault:20. flip_cnt: 23, stem_cnt: 93, fault_cnt:52 +[UP] flip: 13, stem: 3524, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:50 +[UP] flip: 0, stem: 708, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:52 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 4255, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:16 +[UP] flip: 5, stem: 1419, fault:9. flip_cnt: 3, stem_cnt: 94, fault_cnt:40 +[UP] flip: 0, stem: 2134, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:46 +[UP] flip: 0, stem: 711, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 2144, fault:3. flip_cnt: 1, stem_cnt: 91, fault_cnt:21 +[UP] flip: 12, stem: 1, fault:9. flip_cnt: 4, stem_cnt: 95, fault_cnt:36 +[UP] flip: 7, stem: 717, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:49 +[UP] flip: 9, stem: 1432, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:49 +[UP] flip: 0, stem: 2149, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:48 +[UP] flip: 0, stem: 2867, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3606, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:19 +[UP] flip: 10, stem: 3617, fault:9. flip_cnt: 5, stem_cnt: 83, fault_cnt:47 +[UP] flip: 0, stem: 1444, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:60 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 52, stem: 4350, fault:3. flip_cnt: 27, stem_cnt: 90, fault_cnt:85 +[UP] flip: 5, stem: 1453, fault:9. flip_cnt: 2, stem_cnt: 93, fault_cnt:78 +[UP] flip: 0, stem: 729, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:90 +[UP] flip: 0, stem: 726, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:99 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 22, stem: 2192, fault:3. flip_cnt: 11, stem_cnt: 91, fault_cnt:40 +[UP] flip: 24, stem: 2193, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:41 +[UP] flip: 18, stem: 2923, fault:20. flip_cnt: 5, stem_cnt: 93, fault_cnt:36 +[UP] flip: 0, stem: 3664, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:29 +[UP] flip: 0, stem: 3664, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:40 +[UP] flip: 23, stem: 3664, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:37 +[UP] flip: 56, stem: 3, fault:19. flip_cnt: 11, stem_cnt: 93, fault_cnt:49 +[UP] flip: 42, stem: 737, fault:19. flip_cnt: 7, stem_cnt: 95, fault_cnt:58 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 2958, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:32 +[UP] flip: 0, stem: 741, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:45 +[UP] flip: 32, stem: 2, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:59 +[UP] flip: 4, stem: 745, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:63 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 4465, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:30 +[UP] flip: 82, stem: 2237, fault:9. flip_cnt: 37, stem_cnt: 91, fault_cnt:23 +[UP] flip: 4, stem: 748, fault:23. flip_cnt: 2, stem_cnt: 93, fault_cnt:45 +[UP] flip: 9, stem: 745, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 13, stem: 745, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 16, stem: 745, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 16, stem: 745, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 22, stem: 745, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 21, stem: 745, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 42, stem: 745, fault:23. flip_cnt: 5, stem_cnt: 95, fault_cnt:49 +[UP] flip: 50, stem: 745, fault:23. flip_cnt: 5, stem_cnt: 95, fault_cnt:50 +[UP] flip: 100, stem: 746, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:45 +[UP] flip: 33, stem: 756, fault:23. flip_cnt: 4, stem_cnt: 95, fault_cnt:80 +[UP] flip: 90, stem: 2, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:80 +[UP] flip: 51, stem: 2267, fault:20. flip_cnt: 5, stem_cnt: 85, fault_cnt:85 +[UP] flip: 210, stem: 760, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:83 +[UP] flip: 173, stem: 759, fault:19. flip_cnt: 11, stem_cnt: 95, fault_cnt:79 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 1525, fault:3. flip_cnt: 4, stem_cnt: 93, fault_cnt:70 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 3821, fault:3. flip_cnt: 8, stem_cnt: 90, fault_cnt:27 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3065, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:35 +[UP] flip: 7, stem: 776, fault:12. flip_cnt: 3, stem_cnt: 86, fault_cnt:49 +[UP] flip: 14, stem: 2, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:37 +[UP] flip: 159, stem: 771, fault:22. flip_cnt: 37, stem_cnt: 93, fault_cnt:35 +[UP] flip: 43, stem: 3, fault:22. flip_cnt: 9, stem_cnt: 93, fault_cnt:53 +[UP] flip: 12, stem: 2314, fault:22. flip_cnt: 2, stem_cnt: 92, fault_cnt:67 +[UP] flip: 21, stem: 770, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:57 +[UP] flip: 23, stem: 770, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:57 +[UP] flip: 25, stem: 770, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:57 +[UP] flip: 24, stem: 770, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:57 +[UP] flip: 26, stem: 770, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:57 +[UP] flip: 90, stem: 1543, fault:27. flip_cnt: 9, stem_cnt: 93, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 5454, fault:3. flip_cnt: 2, stem_cnt: 88, fault_cnt:43 +[UP] flip: 26, stem: 1561, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:48 +[UP] flip: 0, stem: 3128, fault:20. flip_cnt: 0, stem_cnt: 85, fault_cnt:38 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:52 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 2352, fault:3. flip_cnt: 7, stem_cnt: 93, fault_cnt:71 +[UP] flip: 29, stem: 3925, fault:9. flip_cnt: 10, stem_cnt: 90, fault_cnt:36 +[UP] flip: 23, stem: 2356, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:88 +[UP] flip: 10, stem: 1575, fault:19. flip_cnt: 2, stem_cnt: 93, fault_cnt:36 +[UP] flip: 15, stem: 1575, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:37 +[UP] flip: 10, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 35, stem: 794, fault:3. flip_cnt: 20, stem_cnt: 92, fault_cnt:30 +[UP] flip: 21, stem: 2, fault:10. flip_cnt: 7, stem_cnt: 94, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 69, stem: 4766, fault:3. flip_cnt: 37, stem_cnt: 88, fault_cnt:18 +[UP] flip: 19, stem: 3976, fault:9. flip_cnt: 9, stem_cnt: 89, fault_cnt:78 +[UP] flip: 1, stem: 797, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:11 +[UP] flip: 50, stem: 2, fault:19. flip_cnt: 11, stem_cnt: 94, fault_cnt:14 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3996, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:32 +[UP] flip: 4, stem: 9, fault:3. flip_cnt: 3, stem_cnt: 87, fault_cnt:74 +[UP] flip: 5, stem: 9, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:74 +[UP] flip: 7, stem: 803, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:58 +[UP] flip: 20, stem: 802, fault:23. flip_cnt: 5, stem_cnt: 95, fault_cnt:57 +[UP] flip: 191, stem: 2, fault:23. flip_cnt: 37, stem_cnt: 94, fault_cnt:47 +[UP] flip: 4, stem: 1, fault:23. flip_cnt: 1, stem_cnt: 95, fault_cnt:82 +[UP] flip: 56, stem: 2, fault:20. flip_cnt: 8, stem_cnt: 94, fault_cnt:75 +[UP] flip: 280, stem: 2417, fault:20. flip_cnt: 37, stem_cnt: 92, fault_cnt:82 +[UP] flip: 154, stem: 1, fault:19. flip_cnt: 19, stem_cnt: 95, fault_cnt:52 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 4051, fault:3. flip_cnt: 1, stem_cnt: 90, fault_cnt:90 +[UP] flip: 24, stem: 1621, fault:9. flip_cnt: 9, stem_cnt: 93, fault_cnt:73 +[UP] flip: 11, stem: 1, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:56 +[UP] flip: 15, stem: 1, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 36, stem: 812, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 6, stem: 3, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:90 +[UP] flip: 140, stem: 2450, fault:20. flip_cnt: 19, stem_cnt: 91, fault_cnt:82 +[UP] flip: 66, stem: 2453, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:74 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 828, fault:3. flip_cnt: 0, stem_cnt: 86, fault_cnt:51 +[UP] flip: 0, stem: 2461, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:44 +[UP] flip: 27, stem: 822, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:29 +[UP] flip: 0, stem: 1642, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:54 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 1649, fault:3. flip_cnt: 2, stem_cnt: 93, fault_cnt:43 +[UP] flip: 22, stem: 829, fault:10. flip_cnt: 8, stem_cnt: 91, fault_cnt:26 +[UP] flip: 25, stem: 3, fault:22. flip_cnt: 9, stem_cnt: 93, fault_cnt:49 +[UP] flip: 2, stem: 1, fault:22. flip_cnt: 1, stem_cnt: 95, fault_cnt:92 +[UP] flip: 38, stem: 2, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:86 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 3, fault:3. flip_cnt: 9, stem_cnt: 93, fault_cnt:42 +[UP] flip: 9, stem: 840, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:45 +[UP] flip: 10, stem: 1665, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:28 +[UP] flip: 15, stem: 1, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 37, stem: 3, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:46 +[UP] flip: 6, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:82 +[UP] flip: 84, stem: 833, fault:20. flip_cnt: 15, stem_cnt: 94, fault_cnt:79 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 4197, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:23 +[UP] flip: 5, stem: 842, fault:10. flip_cnt: 2, stem_cnt: 93, fault_cnt:47 +[UP] flip: 0, stem: 1683, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:48 +[UP] flip: 14, stem: 1678, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:32 +[UP] flip: 43, stem: 3, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:45 +[UP] flip: 5, stem: 2, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:86 +[UP] flip: 182, stem: 848, fault:19. flip_cnt: 27, stem_cnt: 92, fault_cnt:73 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 5085, fault:3. flip_cnt: 9, stem_cnt: 87, fault_cnt:30 +[UP] flip: 20, stem: 1703, fault:9. flip_cnt: 7, stem_cnt: 86, fault_cnt:57 +[UP] flip: 6, stem: 850, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 3406, fault:3. flip_cnt: 2, stem_cnt: 90, fault_cnt:18 +[UP] flip: 0, stem: 1705, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:34 +[UP] flip: 6, stem: 1708, fault:23. flip_cnt: 2, stem_cnt: 92, fault_cnt:42 +[UP] flip: 12, stem: 853, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 16, stem: 856, fault:23. flip_cnt: 3, stem_cnt: 94, fault_cnt:33 +[UP] flip: 34, stem: 856, fault:23. flip_cnt: 7, stem_cnt: 94, fault_cnt:38 +[UP] flip: 48, stem: 1703, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:47 +[UP] flip: 14, stem: 2567, fault:28. flip_cnt: 2, stem_cnt: 93, fault_cnt:68 +[UP] flip: 177, stem: 2571, fault:20. flip_cnt: 27, stem_cnt: 93, fault_cnt:84 +[UP] flip: 70, stem: 5133, fault:19. flip_cnt: 9, stem_cnt: 90, fault_cnt:85 +[UP] flip: 104, stem: 5992, fault:19. flip_cnt: 11, stem_cnt: 92, fault_cnt:72 +[UP] flip: 87, stem: 1699, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:73 +[UP] flip: 43, stem: 2567, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1731, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:83 +[UP] flip: 8, stem: 1733, fault:9. flip_cnt: 3, stem_cnt: 93, fault_cnt:35 +[UP] flip: 133, stem: 869, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3477, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:36 +[UP] flip: 34, stem: 5218, fault:9. flip_cnt: 12, stem_cnt: 91, fault_cnt:31 +[UP] flip: 11, stem: 5226, fault:20. flip_cnt: 3, stem_cnt: 85, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 4366, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:30 +[UP] flip: 2, stem: 2622, fault:9. flip_cnt: 1, stem_cnt: 92, fault_cnt:31 +[UP] flip: 0, stem: 3499, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:28 +[UP] flip: 27, stem: 1748, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:29 +[UP] flip: 6, stem: 874, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 6154, fault:3. flip_cnt: 7, stem_cnt: 88, fault_cnt:22 +[UP] flip: 6, stem: 2649, fault:12. flip_cnt: 3, stem_cnt: 84, fault_cnt:37 +[UP] flip: 24, stem: 881, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 33, stem: 2651, fault:3. flip_cnt: 19, stem_cnt: 91, fault_cnt:20 +[UP] flip: 9, stem: 883, fault:11. flip_cnt: 5, stem_cnt: 95, fault_cnt:47 +[UP] flip: 0, stem: 2656, fault:19. flip_cnt: 0, stem_cnt: 92, fault_cnt:50 +[UP] flip: 65, stem: 3545, fault:19. flip_cnt: 15, stem_cnt: 91, fault_cnt:26 +[UP] flip: 0, stem: 4431, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:33 +[UP] flip: 47, stem: 2659, fault:19. flip_cnt: 8, stem_cnt: 93, fault_cnt:36 +[UP] flip: 62, stem: 1, fault:25. flip_cnt: 10, stem_cnt: 95, fault_cnt:40 +[UP] flip: 45, stem: 2, fault:25. flip_cnt: 7, stem_cnt: 94, fault_cnt:39 +[UP] flip: 79, stem: 894, fault:25. flip_cnt: 9, stem_cnt: 92, fault_cnt:33 +[UP] flip: 17, stem: 883, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:44 +[UP] flip: 32, stem: 885, fault:25. flip_cnt: 4, stem_cnt: 95, fault_cnt:62 +[UP] flip: 38, stem: 891, fault:25. flip_cnt: 4, stem_cnt: 95, fault_cnt:54 +[UP] flip: 6, stem: 883, fault:25. flip_cnt: 1, stem_cnt: 95, fault_cnt:84 +[UP] flip: 337, stem: 887, fault:19. flip_cnt: 28, stem_cnt: 93, fault_cnt:69 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 5388, fault:3. flip_cnt: 11, stem_cnt: 90, fault_cnt:37 +[UP] flip: 7, stem: 901, fault:10. flip_cnt: 4, stem_cnt: 93, fault_cnt:40 +[UP] flip: 36, stem: 3, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:42 +[UP] flip: 4, stem: 1, fault:19. flip_cnt: 1, stem_cnt: 95, fault_cnt:74 +[UP] flip: 136, stem: 3, fault:19. flip_cnt: 28, stem_cnt: 93, fault_cnt:61 +[UP] flip: 158, stem: 900, fault:19. flip_cnt: 27, stem_cnt: 95, fault_cnt:52 +[UP] flip: 66, stem: 903, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 24, stem: 0, fault:19. flip_cnt: 3, stem_cnt: 96, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 3628, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 3639, fault:3. flip_cnt: 1, stem_cnt: 89, fault_cnt:20 +[UP] flip: 12, stem: 1824, fault:10. flip_cnt: 7, stem_cnt: 90, fault_cnt:10 +[UP] flip: 9, stem: 910, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 137, stem: 1822, fault:19. flip_cnt: 37, stem_cnt: 93, fault_cnt:35 +[UP] flip: 0, stem: 914, fault:24. flip_cnt: 0, stem_cnt: 94, fault_cnt:50 +[UP] flip: 15, stem: 913, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 18, stem: 913, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 18, stem: 913, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 23, stem: 913, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 47, stem: 913, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:53 +[UP] flip: 20, stem: 913, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 26, stem: 913, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 104, stem: 911, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:49 +[UP] flip: 80, stem: 923, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:74 +[UP] flip: 183, stem: 2, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:89 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6476, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:29 +[UP] flip: 0, stem: 1859, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:37 +[UP] flip: 14, stem: 927, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:48 +[UP] flip: 94, stem: 929, fault:20. flip_cnt: 27, stem_cnt: 93, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 41, stem: 932, fault:3. flip_cnt: 23, stem_cnt: 93, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 22, stem: 3728, fault:3. flip_cnt: 12, stem_cnt: 92, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1869, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:28 +[UP] flip: 0, stem: 936, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:28 +[UP] flip: 4, stem: 938, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:22 +[UP] flip: 0, stem: 2810, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:22 +[UP] flip: 0, stem: 2810, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:22 +[UP] flip: 0, stem: 4687, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:21 +[UP] flip: 181, stem: 1880, fault:19. flip_cnt: 37, stem_cnt: 93, fault_cnt:24 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:25 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 41, stem: 3772, fault:3. flip_cnt: 26, stem_cnt: 92, fault_cnt:48 +[UP] flip: 99, stem: 3776, fault:10. flip_cnt: 37, stem_cnt: 91, fault_cnt:46 +[UP] flip: 10, stem: 1896, fault:19. flip_cnt: 3, stem_cnt: 86, fault_cnt:46 +[UP] flip: 7, stem: 943, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3793, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:45 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:44 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 4756, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:45 +[UP] flip: 29, stem: 953, fault:9. flip_cnt: 11, stem_cnt: 93, fault_cnt:45 +[UP] flip: 0, stem: 953, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3821, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:33 +[UP] flip: 2, stem: 7, fault:9. flip_cnt: 1, stem_cnt: 89, fault_cnt:41 +[UP] flip: 0, stem: 957, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 1919, fault:3. flip_cnt: 3, stem_cnt: 93, fault_cnt:41 +[UP] flip: 0, stem: 961, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:30 +[UP] flip: 0, stem: 963, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:35 +[UP] flip: 11, stem: 962, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:40 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:46 +[UP] flip: 16, stem: 0, fault:20. flip_cnt: 3, stem_cnt: 96, fault_cnt:49 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 3867, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:73 +[UP] flip: 21, stem: 2910, fault:9. flip_cnt: 9, stem_cnt: 84, fault_cnt:76 +[UP] flip: 9, stem: 4840, fault:20. flip_cnt: 3, stem_cnt: 91, fault_cnt:50 +[UP] flip: 13, stem: 4843, fault:20. flip_cnt: 3, stem_cnt: 88, fault_cnt:66 +[UP] flip: 0, stem: 3878, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:65 +[UP] flip: 58, stem: 1944, fault:20. flip_cnt: 11, stem_cnt: 92, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 5839, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:70 +[UP] flip: 5, stem: 4, fault:9. flip_cnt: 2, stem_cnt: 92, fault_cnt:37 +[UP] flip: 67, stem: 3, fault:20. flip_cnt: 23, stem_cnt: 93, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 3910, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:31 +[UP] flip: 14, stem: 2935, fault:10. flip_cnt: 7, stem_cnt: 92, fault_cnt:67 +[UP] flip: 17, stem: 1958, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:17 +[UP] flip: 110, stem: 978, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:23 +[UP] flip: 4, stem: 2933, fault:19. flip_cnt: 1, stem_cnt: 93, fault_cnt:17 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 5901, fault:3. flip_cnt: 0, stem_cnt: 87, fault_cnt:35 +[UP] flip: 6, stem: 9, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:37 +[UP] flip: 0, stem: 4926, fault:20. flip_cnt: 0, stem_cnt: 90, fault_cnt:31 +[UP] flip: 12, stem: 4929, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:42 +[UP] flip: 30, stem: 984, fault:20. flip_cnt: 9, stem_cnt: 94, fault_cnt:43 +[UP] flip: 17, stem: 4929, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:42 +[UP] flip: 0, stem: 4941, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:42 +[UP] flip: 0, stem: 992, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:20 +[UP] flip: 117, stem: 992, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:23 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 2982, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:16 +[UP] flip: 18, stem: 995, fault:9. flip_cnt: 7, stem_cnt: 94, fault_cnt:34 +[UP] flip: 0, stem: 996, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:35 +[UP] flip: 80, stem: 1993, fault:20. flip_cnt: 28, stem_cnt: 92, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 3995, fault:3. flip_cnt: 1, stem_cnt: 89, fault_cnt:54 +[UP] flip: 21, stem: 2998, fault:10. flip_cnt: 9, stem_cnt: 91, fault_cnt:45 +[UP] flip: 9, stem: 9, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:47 +[UP] flip: 0, stem: 4005, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:45 +[UP] flip: 14, stem: 5009, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:47 +[UP] flip: 0, stem: 3007, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 2012, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:70 +[UP] flip: 0, stem: 3019, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:79 +[UP] flip: 0, stem: 1011, fault:11. flip_cnt: 0, stem_cnt: 90, fault_cnt:18 +[UP] flip: 7, stem: 5039, fault:20. flip_cnt: 2, stem_cnt: 89, fault_cnt:11 +[UP] flip: 5, stem: 1, fault:19. flip_cnt: 1, stem_cnt: 95, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 5056, fault:3. flip_cnt: 2, stem_cnt: 90, fault_cnt:19 +[UP] flip: 18, stem: 1011, fault:10. flip_cnt: 7, stem_cnt: 95, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 7099, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:59 +[UP] flip: 0, stem: 1024, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:48 +[UP] flip: 11, stem: 4063, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:45 +[UP] flip: 16, stem: 3046, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:45 +[UP] flip: 21, stem: 3046, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:45 +[UP] flip: 0, stem: 4073, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:51 +[UP] flip: 0, stem: 2036, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:65 +[UP] flip: 0, stem: 1020, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:63 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 5116, fault:3. flip_cnt: 1, stem_cnt: 90, fault_cnt:33 +[UP] flip: 14, stem: 2047, fault:9. flip_cnt: 5, stem_cnt: 94, fault_cnt:51 +[UP] flip: 11, stem: 2051, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:37 +[UP] flip: 32, stem: 5129, fault:20. flip_cnt: 7, stem_cnt: 91, fault_cnt:37 +[UP] flip: 16, stem: 1026, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 6, stem: 1, fault:19. flip_cnt: 1, stem_cnt: 95, fault_cnt:52 +[UP] flip: 205, stem: 2, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:51 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1032, fault:3. flip_cnt: 0, stem_cnt: 94, fault_cnt:31 +[UP] flip: 39, stem: 0, fault:9. flip_cnt: 19, stem_cnt: 96, fault_cnt:40 +[UP] flip: 0, stem: 1034, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:50 +[UP] flip: 0, stem: 3101, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:49 +[UP] flip: 39, stem: 1036, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:61 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 7259, fault:3. flip_cnt: 11, stem_cnt: 89, fault_cnt:28 +[UP] flip: 0, stem: 2075, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:51 +[UP] flip: 0, stem: 2079, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:41 +[UP] flip: 0, stem: 2079, fault:24. flip_cnt: 0, stem_cnt: 94, fault_cnt:48 +[UP] flip: 58, stem: 1040, fault:20. flip_cnt: 12, stem_cnt: 94, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 2087, fault:3. flip_cnt: 3, stem_cnt: 93, fault_cnt:44 +[UP] flip: 0, stem: 2089, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:47 +[UP] flip: 0, stem: 1047, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:41 +[UP] flip: 66, stem: 2092, fault:20. flip_cnt: 15, stem_cnt: 93, fault_cnt:37 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 5247, fault:3. flip_cnt: 4, stem_cnt: 89, fault_cnt:18 +[UP] flip: 8, stem: 2101, fault:9. flip_cnt: 3, stem_cnt: 93, fault_cnt:25 +[UP] flip: 28, stem: 2104, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:39 +[UP] flip: 10, stem: 2, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:53 +[UP] flip: 79, stem: 1052, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:59 +[UP] flip: 42, stem: 2, fault:19. flip_cnt: 9, stem_cnt: 94, fault_cnt:59 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 4225, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:33 +[UP] flip: 0, stem: 3172, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:53 +[UP] flip: 0, stem: 2115, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:56 +[UP] flip: 18, stem: 1059, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:42 +[UP] flip: 10, stem: 1059, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:36 +[UP] flip: 66, stem: 1, fault:20. flip_cnt: 11, stem_cnt: 95, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 5316, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:56 +[UP] flip: 9, stem: 9, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:66 +[UP] flip: 11, stem: 2131, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:51 +[UP] flip: 15, stem: 1, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 38, stem: 3, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:45 +[UP] flip: 6, stem: 2132, fault:24. flip_cnt: 1, stem_cnt: 93, fault_cnt:63 +[UP] flip: 49, stem: 2135, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:82 +[UP] flip: 112, stem: 2, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:84 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 42, stem: 1074, fault:3. flip_cnt: 23, stem_cnt: 93, fault_cnt:36 +[UP] flip: 6, stem: 1074, fault:9. flip_cnt: 2, stem_cnt: 94, fault_cnt:50 +[UP] flip: 15, stem: 4298, fault:20. flip_cnt: 4, stem_cnt: 90, fault_cnt:32 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 3229, fault:3. flip_cnt: 6, stem_cnt: 92, fault_cnt:25 +[UP] flip: 20, stem: 3231, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:88 +[UP] flip: 20, stem: 2162, fault:20. flip_cnt: 7, stem_cnt: 86, fault_cnt:82 +[UP] flip: 18, stem: 4316, fault:20. flip_cnt: 4, stem_cnt: 91, fault_cnt:25 +[UP] flip: 195, stem: 3237, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 5411, fault:3. flip_cnt: 3, stem_cnt: 90, fault_cnt:23 +[UP] flip: 25, stem: 3252, fault:9. flip_cnt: 9, stem_cnt: 90, fault_cnt:29 +[UP] flip: 0, stem: 5421, fault:20. flip_cnt: 0, stem_cnt: 90, fault_cnt:45 +[UP] flip: 31, stem: 4337, fault:19. flip_cnt: 7, stem_cnt: 92, fault_cnt:69 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 5437, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:49 +[UP] flip: 0, stem: 4353, fault:9. flip_cnt: 0, stem_cnt: 90, fault_cnt:53 +[UP] flip: 0, stem: 1091, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:37 +[UP] flip: 14, stem: 2177, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 26, stem: 4369, fault:3. flip_cnt: 15, stem_cnt: 91, fault_cnt:28 +[UP] flip: 8, stem: 1095, fault:12. flip_cnt: 4, stem_cnt: 93, fault_cnt:46 +[UP] flip: 40, stem: 2, fault:18. flip_cnt: 12, stem_cnt: 94, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 22, stem: 4386, fault:3. flip_cnt: 11, stem_cnt: 90, fault_cnt:42 +[UP] flip: 21, stem: 2, fault:10. flip_cnt: 7, stem_cnt: 94, fault_cnt:58 +[UP] flip: 57, stem: 2, fault:18. flip_cnt: 15, stem_cnt: 94, fault_cnt:61 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 4403, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:62 +[UP] flip: 18, stem: 1, fault:9. flip_cnt: 6, stem_cnt: 95, fault_cnt:44 +[UP] flip: 12, stem: 1103, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:53 +[UP] flip: 16, stem: 2204, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:50 +[UP] flip: 0, stem: 3308, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:50 +[UP] flip: 0, stem: 4411, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:50 +[UP] flip: 0, stem: 5517, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:50 +[UP] flip: 0, stem: 1107, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:50 +[UP] flip: 0, stem: 2217, fault:19. flip_cnt: 0, stem_cnt: 92, fault_cnt:52 +[UP] flip: 0, stem: 3324, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:54 +[UP] flip: 0, stem: 4432, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:54 +[UP] flip: 0, stem: 5543, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:54 +[UP] flip: 0, stem: 6654, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:53 +[UP] flip: 30, stem: 8877, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:51 +[UP] flip: 139, stem: 9992, fault:19. flip_cnt: 11, stem_cnt: 93, fault_cnt:52 +[UP] flip: 57, stem: 8878, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:55 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 2235, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:19 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3359, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:29 +[UP] flip: 26, stem: 4481, fault:9. flip_cnt: 9, stem_cnt: 90, fault_cnt:31 +[UP] flip: 3, stem: 2243, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:34 +[UP] flip: 32, stem: 5605, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:20 +[UP] flip: 13, stem: 4483, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:44 +[UP] flip: 58, stem: 1122, fault:19. flip_cnt: 10, stem_cnt: 95, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 3, fault:3. flip_cnt: 2, stem_cnt: 93, fault_cnt:37 +[UP] flip: 0, stem: 1128, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:37 +[UP] flip: 0, stem: 1129, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:41 +[UP] flip: 0, stem: 2257, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:41 +[UP] flip: 0, stem: 3385, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:35 +[UP] flip: 0, stem: 4517, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:34 +[UP] flip: 17, stem: 6778, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:32 +[UP] flip: 0, stem: 6780, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 6811, fault:3. flip_cnt: 4, stem_cnt: 89, fault_cnt:35 +[UP] flip: 9, stem: 2274, fault:10. flip_cnt: 4, stem_cnt: 92, fault_cnt:31 +[UP] flip: 120, stem: 2276, fault:19. flip_cnt: 37, stem_cnt: 92, fault_cnt:37 +[UP] flip: 13, stem: 3408, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:49 +[UP] flip: 21, stem: 3418, fault:19. flip_cnt: 4, stem_cnt: 92, fault_cnt:60 +[UP] flip: 20, stem: 3415, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:64 +[UP] flip: 8, stem: 4555, fault:19. flip_cnt: 1, stem_cnt: 93, fault_cnt:60 +[UP] flip: 50, stem: 4561, fault:19. flip_cnt: 7, stem_cnt: 93, fault_cnt:57 +[UP] flip: 39, stem: 2278, fault:28. flip_cnt: 5, stem_cnt: 94, fault_cnt:61 +[UP] flip: 24, stem: 2279, fault:28. flip_cnt: 3, stem_cnt: 94, fault_cnt:57 +[UP] flip: 22, stem: 1135, fault:28. flip_cnt: 3, stem_cnt: 95, fault_cnt:60 +[UP] flip: 27, stem: 1135, fault:28. flip_cnt: 3, stem_cnt: 95, fault_cnt:60 +[UP] flip: 25, stem: 1135, fault:28. flip_cnt: 3, stem_cnt: 95, fault_cnt:60 +[UP] flip: 97, stem: 1143, fault:28. flip_cnt: 9, stem_cnt: 93, fault_cnt:59 +[UP] flip: 15, stem: 4569, fault:19. flip_cnt: 1, stem_cnt: 91, fault_cnt:62 +[UP] flip: 11, stem: 1150, fault:35. flip_cnt: 2, stem_cnt: 95, fault_cnt:91 +[UP] flip: 20, stem: 3420, fault:19. flip_cnt: 2, stem_cnt: 92, fault_cnt:88 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 4614, fault:3. flip_cnt: 3, stem_cnt: 90, fault_cnt:23 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 6933, fault:3. flip_cnt: 9, stem_cnt: 87, fault_cnt:40 +[UP] flip: 3, stem: 3470, fault:10. flip_cnt: 1, stem_cnt: 91, fault_cnt:24 +[UP] flip: 0, stem: 1158, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:14 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:21 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3481, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:48 +[UP] flip: 9, stem: 1, fault:9. flip_cnt: 3, stem_cnt: 95, fault_cnt:79 +[UP] flip: 38, stem: 1163, fault:20. flip_cnt: 10, stem_cnt: 94, fault_cnt:57 +[UP] flip: 0, stem: 2325, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:70 +[UP] flip: 94, stem: 4648, fault:20. flip_cnt: 18, stem_cnt: 93, fault_cnt:61 +[UP] flip: 0, stem: 3496, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:48 +[UP] flip: 30, stem: 1166, fault:19. flip_cnt: 4, stem_cnt: 95, fault_cnt:52 +[UP] flip: 24, stem: 0, fault:19. flip_cnt: 3, stem_cnt: 96, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 7015, fault:3. flip_cnt: 2, stem_cnt: 89, fault_cnt:17 +[UP] flip: 20, stem: 2341, fault:10. flip_cnt: 7, stem_cnt: 93, fault_cnt:40 +[UP] flip: 135, stem: 1173, fault:19. flip_cnt: 37, stem_cnt: 93, fault_cnt:31 +[UP] flip: 13, stem: 1169, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 14, stem: 1169, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 18, stem: 1169, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 23, stem: 1169, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 17, stem: 1169, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 38, stem: 1169, fault:19. flip_cnt: 5, stem_cnt: 95, fault_cnt:50 +[UP] flip: 21, stem: 1169, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 41, stem: 1169, fault:19. flip_cnt: 5, stem_cnt: 95, fault_cnt:50 +[UP] flip: 99, stem: 1172, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:45 +[UP] flip: 12, stem: 1182, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:82 +[UP] flip: 257, stem: 1170, fault:19. flip_cnt: 19, stem_cnt: 94, fault_cnt:81 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 7106, fault:3. flip_cnt: 1, stem_cnt: 88, fault_cnt:44 +[UP] flip: 20, stem: 4739, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:25 +[UP] flip: 0, stem: 1187, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:54 +[UP] flip: 152, stem: 4742, fault:20. flip_cnt: 37, stem_cnt: 92, fault_cnt:53 +[UP] flip: 8, stem: 1185, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:49 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 25, stem: 1, fault:3. flip_cnt: 16, stem_cnt: 95, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 4771, fault:3. flip_cnt: 1, stem_cnt: 89, fault_cnt:33 +[UP] flip: 30, stem: 1, fault:10. flip_cnt: 11, stem_cnt: 95, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 3, fault:3. flip_cnt: 9, stem_cnt: 93, fault_cnt:39 +[UP] flip: 8, stem: 1205, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:38 +[UP] flip: 0, stem: 4789, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:29 +[UP] flip: 30, stem: 3592, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:32 +[UP] flip: 0, stem: 4789, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:36 +[UP] flip: 24, stem: 4791, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:29 +[UP] flip: 0, stem: 5993, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:23 +[UP] flip: 0, stem: 7193, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:23 +[UP] flip: 0, stem: 8395, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:23 +[UP] flip: 0, stem: 9598, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:23 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 42, stem: 4824, fault:3. flip_cnt: 24, stem_cnt: 92, fault_cnt:68 +[UP] flip: 9, stem: 2421, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:75 +[UP] flip: 0, stem: 1209, fault:23. flip_cnt: 0, stem_cnt: 94, fault_cnt:63 +[UP] flip: 172, stem: 2, fault:23. flip_cnt: 37, stem_cnt: 94, fault_cnt:52 +[UP] flip: 4, stem: 3, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:86 +[UP] flip: 11, stem: 3, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:86 +[UP] flip: 112, stem: 2425, fault:20. flip_cnt: 15, stem_cnt: 93, fault_cnt:81 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:92 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 2431, fault:3. flip_cnt: 2, stem_cnt: 93, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 4869, fault:3. flip_cnt: 4, stem_cnt: 91, fault_cnt:48 +[UP] flip: 19, stem: 2437, fault:9. flip_cnt: 7, stem_cnt: 93, fault_cnt:38 +[UP] flip: 0, stem: 6094, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:40 +[UP] flip: 48, stem: 2441, fault:19. flip_cnt: 10, stem_cnt: 93, fault_cnt:32 +[UP] flip: 0, stem: 1220, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:58 +[UP] flip: 0, stem: 1220, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:58 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 48, stem: 4898, fault:3. flip_cnt: 37, stem_cnt: 90, fault_cnt:14 +[UP] flip: 7, stem: 2451, fault:9. flip_cnt: 4, stem_cnt: 93, fault_cnt:62 +[UP] flip: 23, stem: 3676, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:42 +[UP] flip: 37, stem: 2454, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:44 +[UP] flip: 0, stem: 1224, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:55 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6151, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:47 +[UP] flip: 33, stem: 0, fault:9. flip_cnt: 12, stem_cnt: 96, fault_cnt:68 +[UP] flip: 0, stem: 1234, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:62 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:70 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6176, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:35 +[UP] flip: 13, stem: 0, fault:9. flip_cnt: 7, stem_cnt: 96, fault_cnt:41 +[UP] flip: 0, stem: 1239, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:38 +[UP] flip: 0, stem: 3, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:36 +[UP] flip: 14, stem: 2479, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:33 +[UP] flip: 0, stem: 1239, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:47 +[UP] flip: 0, stem: 1239, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 3729, fault:3. flip_cnt: 3, stem_cnt: 93, fault_cnt:28 +[UP] flip: 4, stem: 2, fault:9. flip_cnt: 2, stem_cnt: 94, fault_cnt:46 +[UP] flip: 0, stem: 1246, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:55 +[UP] flip: 0, stem: 1247, fault:24. flip_cnt: 0, stem_cnt: 94, fault_cnt:60 +[UP] flip: 15, stem: 1, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 47, stem: 3, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:47 +[UP] flip: 4, stem: 2491, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:80 +[UP] flip: 9, stem: 2491, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:80 +[UP] flip: 8, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:94 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 1, stem: 8773, fault:3. flip_cnt: 1, stem_cnt: 87, fault_cnt:27 +[UP] flip: 20, stem: 1255, fault:10. flip_cnt: 9, stem_cnt: 93, fault_cnt:41 +[UP] flip: 10, stem: 1261, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:42 +[UP] flip: 0, stem: 3769, fault:19. flip_cnt: 0, stem_cnt: 92, fault_cnt:27 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 65, stem: 2517, fault:3. flip_cnt: 37, stem_cnt: 93, fault_cnt:28 +[UP] flip: 2, stem: 1260, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:31 +[UP] flip: 14, stem: 6299, fault:20. flip_cnt: 4, stem_cnt: 90, fault_cnt:13 +[UP] flip: 13, stem: 3780, fault:19. flip_cnt: 3, stem_cnt: 93, fault_cnt:30 +[UP] flip: 40, stem: 1265, fault:19. flip_cnt: 9, stem_cnt: 92, fault_cnt:33 +[UP] flip: 0, stem: 2526, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:80 +[UP] flip: 146, stem: 3789, fault:20. flip_cnt: 31, stem_cnt: 92, fault_cnt:76 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 66, stem: 6332, fault:3. flip_cnt: 37, stem_cnt: 89, fault_cnt:17 +[UP] flip: 22, stem: 1270, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:51 +[UP] flip: 3, stem: 2534, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:51 +[UP] flip: 30, stem: 1269, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:73 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 38, stem: 2, fault:3. flip_cnt: 23, stem_cnt: 94, fault_cnt:25 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 6374, fault:3. flip_cnt: 3, stem_cnt: 82, fault_cnt:32 +[UP] flip: 19, stem: 6369, fault:10. flip_cnt: 9, stem_cnt: 90, fault_cnt:42 +[UP] flip: 0, stem: 1276, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6386, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:52 +[UP] flip: 3, stem: 3835, fault:9. flip_cnt: 1, stem_cnt: 92, fault_cnt:54 +[UP] flip: 22, stem: 6393, fault:20. flip_cnt: 9, stem_cnt: 90, fault_cnt:36 +[UP] flip: 14, stem: 1285, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:48 +[UP] flip: 17, stem: 1283, fault:19. flip_cnt: 4, stem_cnt: 93, fault_cnt:36 +[UP] flip: 20, stem: 2559, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 6420, fault:3. flip_cnt: 7, stem_cnt: 91, fault_cnt:37 +[UP] flip: 45, stem: 2572, fault:10. flip_cnt: 23, stem_cnt: 92, fault_cnt:36 +[UP] flip: 0, stem: 3859, fault:19. flip_cnt: 0, stem_cnt: 92, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6441, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:19 +[UP] flip: 12, stem: 1297, fault:4. flip_cnt: 7, stem_cnt: 86, fault_cnt:60 +[UP] flip: 4, stem: 1291, fault:10. flip_cnt: 2, stem_cnt: 94, fault_cnt:48 +[UP] flip: 85, stem: 1288, fault:19. flip_cnt: 27, stem_cnt: 95, fault_cnt:40 +[UP] flip: 33, stem: 1290, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:26 +[UP] flip: 6, stem: 3, fault:19. flip_cnt: 1, stem_cnt: 93, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 3886, fault:3. flip_cnt: 1, stem_cnt: 92, fault_cnt:29 +[UP] flip: 7, stem: 9, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:36 +[UP] flip: 11, stem: 5190, fault:20. flip_cnt: 4, stem_cnt: 90, fault_cnt:20 +[UP] flip: 0, stem: 3891, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:18 +[UP] flip: 0, stem: 3894, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:18 +[UP] flip: 0, stem: 6489, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:18 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 11, stem: 3, fault:3. flip_cnt: 9, stem_cnt: 93, fault_cnt:45 +[UP] flip: 8, stem: 1312, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:47 +[UP] flip: 0, stem: 5217, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 7837, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:31 +[UP] flip: 3, stem: 2616, fault:12. flip_cnt: 2, stem_cnt: 92, fault_cnt:47 +[UP] flip: 9, stem: 1307, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 125, stem: 2, fault:22. flip_cnt: 37, stem_cnt: 94, fault_cnt:47 +[UP] flip: 5, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:65 +[UP] flip: 12, stem: 1, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:65 +[UP] flip: 18, stem: 1, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:59 +[UP] flip: 19, stem: 1, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 64, stem: 3, fault:26. flip_cnt: 9, stem_cnt: 93, fault_cnt:54 +[UP] flip: 10, stem: 2624, fault:26. flip_cnt: 1, stem_cnt: 94, fault_cnt:60 +[UP] flip: 113, stem: 3942, fault:20. flip_cnt: 11, stem_cnt: 92, fault_cnt:52 +[UP] flip: 120, stem: 1318, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:53 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 5277, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:36 +[UP] flip: 3, stem: 1322, fault:9. flip_cnt: 1, stem_cnt: 93, fault_cnt:26 +[UP] flip: 55, stem: 5283, fault:20. flip_cnt: 15, stem_cnt: 92, fault_cnt:18 +[UP] flip: 31, stem: 3968, fault:20. flip_cnt: 7, stem_cnt: 91, fault_cnt:33 +[UP] flip: 12, stem: 1325, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:41 +[UP] flip: 44, stem: 2640, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:45 +[UP] flip: 122, stem: 1321, fault:19. flip_cnt: 19, stem_cnt: 93, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 7963, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:30 +[UP] flip: 9, stem: 2663, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:45 +[UP] flip: 0, stem: 1330, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:51 +[UP] flip: 20, stem: 0, fault:20. flip_cnt: 4, stem_cnt: 96, fault_cnt:44 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1333, fault:3. flip_cnt: 0, stem_cnt: 94, fault_cnt:21 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 5337, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:38 +[UP] flip: 20, stem: 2670, fault:9. flip_cnt: 7, stem_cnt: 94, fault_cnt:38 +[UP] flip: 0, stem: 1337, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:35 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 5357, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:66 +[UP] flip: 9, stem: 1342, fault:9. flip_cnt: 3, stem_cnt: 93, fault_cnt:39 +[UP] flip: 121, stem: 2681, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:35 +[UP] flip: 0, stem: 1340, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 22, stem: 4033, fault:3. flip_cnt: 14, stem_cnt: 92, fault_cnt:67 +[UP] flip: 9, stem: 1346, fault:9. flip_cnt: 3, stem_cnt: 94, fault_cnt:64 +[UP] flip: 115, stem: 1348, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:59 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 8090, fault:3. flip_cnt: 4, stem_cnt: 88, fault_cnt:72 +[UP] flip: 0, stem: 1350, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:72 +[UP] flip: 0, stem: 1350, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:74 +[UP] flip: 0, stem: 1349, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:82 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 5412, fault:3. flip_cnt: 7, stem_cnt: 92, fault_cnt:38 +[UP] flip: 9, stem: 1363, fault:10. flip_cnt: 3, stem_cnt: 86, fault_cnt:43 +[UP] flip: 0, stem: 2711, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:44 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 10, stem: 1359, fault:3. flip_cnt: 9, stem_cnt: 93, fault_cnt:37 +[UP] flip: 0, stem: 1359, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:37 +[UP] flip: 0, stem: 1360, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9528, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:59 +[UP] flip: 12, stem: 1, fault:9. flip_cnt: 4, stem_cnt: 95, fault_cnt:30 +[UP] flip: 0, stem: 2725, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:35 +[UP] flip: 0, stem: 2727, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:37 +[UP] flip: 0, stem: 4090, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:35 +[UP] flip: 0, stem: 5456, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 4105, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:89 +[UP] flip: 86, stem: 2739, fault:10. flip_cnt: 31, stem_cnt: 93, fault_cnt:66 +[UP] flip: 0, stem: 1371, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:24 +[UP] flip: 0, stem: 2741, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:24 +[UP] flip: 4, stem: 1369, fault:19. flip_cnt: 1, stem_cnt: 95, fault_cnt:17 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 1375, fault:3. flip_cnt: 9, stem_cnt: 94, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6881, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:66 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 4135, fault:3. flip_cnt: 7, stem_cnt: 92, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9664, fault:3. flip_cnt: 0, stem_cnt: 85, fault_cnt:60 +[UP] flip: 0, stem: 9669, fault:9. flip_cnt: 0, stem_cnt: 87, fault_cnt:51 +[UP] flip: 0, stem: 8288, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:54 +[UP] flip: 37, stem: 6908, fault:19. flip_cnt: 9, stem_cnt: 91, fault_cnt:23 +[UP] flip: 0, stem: 9667, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:51 +[UP] flip: 0, stem: 5528, fault:19. flip_cnt: 0, stem_cnt: 92, fault_cnt:44 +[UP] flip: 51, stem: 5524, fault:19. flip_cnt: 9, stem_cnt: 92, fault_cnt:45 +[UP] flip: 13, stem: 9667, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:42 +[UP] flip: 15, stem: 9667, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:42 +[UP] flip: 18, stem: 9667, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:42 +[UP] flip: 0, stem: 4160, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:27 +[UP] flip: 172, stem: 2, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 4181, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:20 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 21, stem: 4187, fault:3. flip_cnt: 15, stem_cnt: 91, fault_cnt:43 +[UP] flip: 27, stem: 2795, fault:12. flip_cnt: 9, stem_cnt: 91, fault_cnt:50 +[UP] flip: 11, stem: 2795, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:60 +[UP] flip: 0, stem: 4200, fault:24. flip_cnt: 0, stem_cnt: 85, fault_cnt:64 +[UP] flip: 13, stem: 8389, fault:24. flip_cnt: 3, stem_cnt: 91, fault_cnt:55 +[UP] flip: 10, stem: 8389, fault:24. flip_cnt: 3, stem_cnt: 93, fault_cnt:55 +[UP] flip: 15, stem: 2798, fault:25. flip_cnt: 2, stem_cnt: 93, fault_cnt:47 +[UP] flip: 14, stem: 2799, fault:25. flip_cnt: 2, stem_cnt: 93, fault_cnt:47 +[UP] flip: 14, stem: 4201, fault:25. flip_cnt: 2, stem_cnt: 93, fault_cnt:47 +[UP] flip: 18, stem: 2802, fault:25. flip_cnt: 3, stem_cnt: 94, fault_cnt:45 +[UP] flip: 21, stem: 2803, fault:25. flip_cnt: 3, stem_cnt: 94, fault_cnt:50 +[UP] flip: 34, stem: 1398, fault:25. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 24, stem: 1398, fault:25. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 32, stem: 1398, fault:25. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 10, stem: 2804, fault:25. flip_cnt: 1, stem_cnt: 94, fault_cnt:70 +[UP] flip: 283, stem: 1397, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:77 +[UP] flip: 100, stem: 2809, fault:20. flip_cnt: 7, stem_cnt: 92, fault_cnt:67 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 21, stem: 7066, fault:3. flip_cnt: 11, stem_cnt: 90, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 2, fault:3. flip_cnt: 4, stem_cnt: 94, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 5669, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:14 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8515, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 8527, fault:3. flip_cnt: 2, stem_cnt: 89, fault_cnt:24 +[UP] flip: 11, stem: 1423, fault:9. flip_cnt: 4, stem_cnt: 94, fault_cnt:58 +[UP] flip: 87, stem: 2845, fault:20. flip_cnt: 24, stem_cnt: 93, fault_cnt:52 +[UP] flip: 0, stem: 2849, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:45 +[UP] flip: 15, stem: 5694, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:44 +[UP] flip: 43, stem: 2846, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 7141, fault:3. flip_cnt: 3, stem_cnt: 90, fault_cnt:28 +[UP] flip: 0, stem: 1430, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:50 +[UP] flip: 0, stem: 1431, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:47 +[UP] flip: 0, stem: 1433, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:51 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 9, stem: 5739, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:26 +[UP] flip: 8, stem: 2869, fault:9. flip_cnt: 3, stem_cnt: 94, fault_cnt:39 +[UP] flip: 0, stem: 1436, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:39 +[UP] flip: 57, stem: 1436, fault:20. flip_cnt: 16, stem_cnt: 95, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1441, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:28 +[UP] flip: 0, stem: 1441, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:38 +[UP] flip: 76, stem: 1443, fault:24. flip_cnt: 28, stem_cnt: 93, fault_cnt:41 +[UP] flip: 45, stem: 1441, fault:24. flip_cnt: 10, stem_cnt: 95, fault_cnt:48 +[UP] flip: 31, stem: 1442, fault:24. flip_cnt: 7, stem_cnt: 94, fault_cnt:43 +[UP] flip: 56, stem: 1441, fault:24. flip_cnt: 10, stem_cnt: 95, fault_cnt:48 +[UP] flip: 20, stem: 1445, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:70 +[UP] flip: 190, stem: 1444, fault:20. flip_cnt: 27, stem_cnt: 92, fault_cnt:54 +[UP] flip: 21, stem: 2895, fault:19. flip_cnt: 3, stem_cnt: 93, fault_cnt:55 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8695, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:17 +[UP] flip: 6, stem: 9, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:51 +[UP] flip: 13, stem: 4355, fault:20. flip_cnt: 4, stem_cnt: 91, fault_cnt:33 +[UP] flip: 44, stem: 2904, fault:20. flip_cnt: 10, stem_cnt: 94, fault_cnt:46 +[UP] flip: 0, stem: 1452, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 2919, fault:3. flip_cnt: 3, stem_cnt: 85, fault_cnt:35 +[UP] flip: 0, stem: 7279, fault:9. flip_cnt: 0, stem_cnt: 91, fault_cnt:33 +[UP] flip: 0, stem: 4369, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:35 +[UP] flip: 14, stem: 5829, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:36 +[UP] flip: 14, stem: 2919, fault:19. flip_cnt: 3, stem_cnt: 93, fault_cnt:23 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 9, stem: 4392, fault:3. flip_cnt: 5, stem_cnt: 84, fault_cnt:60 +[UP] flip: 0, stem: 7311, fault:9. flip_cnt: 0, stem_cnt: 90, fault_cnt:80 +[UP] flip: 47, stem: 5854, fault:20. flip_cnt: 15, stem_cnt: 90, fault_cnt:45 +[UP] flip: 22, stem: 2928, fault:19. flip_cnt: 7, stem_cnt: 93, fault_cnt:53 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 13195, fault:3. flip_cnt: 0, stem_cnt: 86, fault_cnt:61 +[UP] flip: 3, stem: 5867, fault:9. flip_cnt: 1, stem_cnt: 92, fault_cnt:70 +[UP] flip: 10, stem: 2936, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:48 +[UP] flip: 19, stem: 1470, fault:20. flip_cnt: 5, stem_cnt: 94, fault_cnt:59 +[UP] flip: 15, stem: 2939, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:54 +[UP] flip: 64, stem: 5877, fault:20. flip_cnt: 11, stem_cnt: 92, fault_cnt:40 +[UP] flip: 3, stem: 2938, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:57 +[UP] flip: 12, stem: 0, fault:20. flip_cnt: 3, stem_cnt: 96, fault_cnt:60 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 11801, fault:3. flip_cnt: 7, stem_cnt: 87, fault_cnt:29 +[UP] flip: 4, stem: 2953, fault:9. flip_cnt: 2, stem_cnt: 93, fault_cnt:63 +[UP] flip: 11, stem: 4437, fault:20. flip_cnt: 3, stem_cnt: 85, fault_cnt:65 +[UP] flip: 19, stem: 2953, fault:24. flip_cnt: 5, stem_cnt: 94, fault_cnt:57 +[UP] flip: 18, stem: 1475, fault:24. flip_cnt: 4, stem_cnt: 95, fault_cnt:50 +[UP] flip: 6, stem: 1477, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:78 +[UP] flip: 10, stem: 2953, fault:27. flip_cnt: 2, stem_cnt: 94, fault_cnt:78 +[UP] flip: 5, stem: 1476, fault:27. flip_cnt: 2, stem_cnt: 94, fault_cnt:78 +[UP] flip: 17, stem: 1476, fault:27. flip_cnt: 2, stem_cnt: 94, fault_cnt:76 +[UP] flip: 18, stem: 1476, fault:27. flip_cnt: 2, stem_cnt: 94, fault_cnt:77 +[UP] flip: 19, stem: 1476, fault:27. flip_cnt: 2, stem_cnt: 94, fault_cnt:78 +[UP] flip: 72, stem: 2944, fault:27. flip_cnt: 9, stem_cnt: 93, fault_cnt:73 +[UP] flip: 11, stem: 5914, fault:27. flip_cnt: 1, stem_cnt: 86, fault_cnt:83 +[UP] flip: 39, stem: 2963, fault:34. flip_cnt: 4, stem_cnt: 94, fault_cnt:71 +[UP] flip: 5, stem: 2954, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:108 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 5973, fault:3. flip_cnt: 3, stem_cnt: 83, fault_cnt:32 +[UP] flip: 10, stem: 4476, fault:9. flip_cnt: 4, stem_cnt: 92, fault_cnt:30 +[UP] flip: 115, stem: 4478, fault:20. flip_cnt: 37, stem_cnt: 92, fault_cnt:31 +[UP] flip: 36, stem: 4479, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:37 +[UP] flip: 8, stem: 5979, fault:20. flip_cnt: 2, stem_cnt: 91, fault_cnt:45 +[UP] flip: 151, stem: 2990, fault:20. flip_cnt: 27, stem_cnt: 94, fault_cnt:74 +[UP] flip: 43, stem: 1497, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:80 +[UP] flip: 87, stem: 1499, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:57 +[UP] flip: 115, stem: 1500, fault:20. flip_cnt: 15, stem_cnt: 94, fault_cnt:54 +[UP] flip: 64, stem: 1499, fault:20. flip_cnt: 7, stem_cnt: 95, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3005, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:41 +[UP] flip: 0, stem: 1504, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:49 +[UP] flip: 0, stem: 1505, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:43 +[UP] flip: 0, stem: 1506, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:52 +[UP] flip: 17, stem: 0, fault:20. flip_cnt: 4, stem_cnt: 96, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1509, fault:3. flip_cnt: 0, stem_cnt: 94, fault_cnt:20 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 10571, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:23 +[UP] flip: 8, stem: 1520, fault:10. flip_cnt: 3, stem_cnt: 86, fault_cnt:36 +[UP] flip: 0, stem: 3025, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:44 +[UP] flip: 14, stem: 1512, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:43 +[UP] flip: 22, stem: 1511, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:32 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 3033, fault:3. flip_cnt: 6, stem_cnt: 93, fault_cnt:71 +[UP] flip: 0, stem: 1518, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:77 +[UP] flip: 47, stem: 9107, fault:20. flip_cnt: 12, stem_cnt: 90, fault_cnt:21 +[UP] flip: 136, stem: 1521, fault:19. flip_cnt: 37, stem_cnt: 93, fault_cnt:39 +[UP] flip: 0, stem: 1518, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 6089, fault:3. flip_cnt: 3, stem_cnt: 91, fault_cnt:19 +[UP] flip: 5, stem: 1525, fault:10. flip_cnt: 2, stem_cnt: 93, fault_cnt:45 +[UP] flip: 8, stem: 1525, fault:22. flip_cnt: 2, stem_cnt: 94, fault_cnt:57 +[UP] flip: 17, stem: 1525, fault:22. flip_cnt: 4, stem_cnt: 95, fault_cnt:60 +[UP] flip: 14, stem: 1525, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:61 +[UP] flip: 14, stem: 1523, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 19, stem: 1523, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 20, stem: 1523, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 15, stem: 1523, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 22, stem: 1523, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 28, stem: 1523, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 10, stem: 3055, fault:22. flip_cnt: 1, stem_cnt: 94, fault_cnt:53 +[UP] flip: 148, stem: 1, fault:19. flip_cnt: 13, stem_cnt: 95, fault_cnt:78 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 4608, fault:3. flip_cnt: 2, stem_cnt: 93, fault_cnt:79 +[UP] flip: 34, stem: 6149, fault:9. flip_cnt: 12, stem_cnt: 91, fault_cnt:37 +[UP] flip: 59, stem: 3076, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:55 +[UP] flip: 14, stem: 1540, fault:24. flip_cnt: 3, stem_cnt: 94, fault_cnt:50 +[UP] flip: 15, stem: 3076, fault:24. flip_cnt: 3, stem_cnt: 94, fault_cnt:52 +[UP] flip: 31, stem: 1536, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:59 +[UP] flip: 13, stem: 1536, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:56 +[UP] flip: 15, stem: 1536, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:56 +[UP] flip: 47, stem: 1536, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:59 +[UP] flip: 46, stem: 1536, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:60 +[UP] flip: 42, stem: 1536, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:59 +[UP] flip: 94, stem: 3075, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:55 +[UP] flip: 50, stem: 3084, fault:24. flip_cnt: 4, stem_cnt: 95, fault_cnt:99 +[UP] flip: 420, stem: 1537, fault:24. flip_cnt: 37, stem_cnt: 94, fault_cnt:68 +[UP] flip: 2, stem: 1538, fault:24. flip_cnt: 1, stem_cnt: 95, fault_cnt:103 +[UP] flip: 104, stem: 3076, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:98 +[UP] flip: 230, stem: 1539, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:101 +[UP] flip: 309, stem: 1540, fault:19. flip_cnt: 19, stem_cnt: 93, fault_cnt:94 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9331, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:53 +[UP] flip: 0, stem: 1557, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:51 +[UP] flip: 8, stem: 1558, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:55 +[UP] flip: 11, stem: 1558, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 16, stem: 1557, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:54 +[UP] flip: 51, stem: 3117, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:46 +[UP] flip: 7, stem: 7789, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:59 +[UP] flip: 3, stem: 9354, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:61 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3130, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:38 +[UP] flip: 6, stem: 1574, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:36 +[UP] flip: 0, stem: 7831, fault:20. flip_cnt: 0, stem_cnt: 90, fault_cnt:31 +[UP] flip: 11, stem: 6269, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:36 +[UP] flip: 13, stem: 4702, fault:19. flip_cnt: 3, stem_cnt: 93, fault_cnt:34 +[UP] flip: 17, stem: 4708, fault:19. flip_cnt: 3, stem_cnt: 92, fault_cnt:14 +[UP] flip: 57, stem: 4703, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:31 +[UP] flip: 32, stem: 1567, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:70 +[UP] flip: 53, stem: 14141, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:71 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 12593, fault:3. flip_cnt: 4, stem_cnt: 87, fault_cnt:22 +[UP] flip: 23, stem: 3151, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:67 +[UP] flip: 0, stem: 4727, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:35 +[UP] flip: 16, stem: 4732, fault:19. flip_cnt: 4, stem_cnt: 92, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11054, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:32 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 20, stem: 1583, fault:3. flip_cnt: 11, stem_cnt: 93, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 3167, fault:3. flip_cnt: 4, stem_cnt: 93, fault_cnt:24 +[UP] flip: 5, stem: 1585, fault:9. flip_cnt: 2, stem_cnt: 94, fault_cnt:37 +[UP] flip: 51, stem: 3171, fault:20. flip_cnt: 23, stem_cnt: 93, fault_cnt:37 +[UP] flip: 0, stem: 3173, fault:24. flip_cnt: 0, stem_cnt: 93, fault_cnt:46 +[UP] flip: 0, stem: 1588, fault:24. flip_cnt: 0, stem_cnt: 94, fault_cnt:43 +[UP] flip: 9, stem: 3170, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:46 +[UP] flip: 15, stem: 1589, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 67, stem: 3, fault:27. flip_cnt: 9, stem_cnt: 93, fault_cnt:43 +[UP] flip: 20, stem: 1591, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:86 +[UP] flip: 23, stem: 1586, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:101 +[UP] flip: 177, stem: 3179, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:93 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 1599, fault:3. flip_cnt: 7, stem_cnt: 91, fault_cnt:20 +[UP] flip: 43, stem: 1598, fault:10. flip_cnt: 20, stem_cnt: 93, fault_cnt:36 +[UP] flip: 26, stem: 2, fault:18. flip_cnt: 9, stem_cnt: 94, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3199, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:49 +[UP] flip: 0, stem: 4801, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:49 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8011, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:38 +[UP] flip: 0, stem: 6419, fault:9. flip_cnt: 0, stem_cnt: 84, fault_cnt:42 +[UP] flip: 0, stem: 8019, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:44 +[UP] flip: 8, stem: 8024, fault:20. flip_cnt: 2, stem_cnt: 91, fault_cnt:33 +[UP] flip: 0, stem: 3210, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:46 +[UP] flip: 0, stem: 3212, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 4828, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:43 +[UP] flip: 0, stem: 1619, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:40 +[UP] flip: 0, stem: 4834, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:35 +[UP] flip: 12, stem: 3222, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:34 +[UP] flip: 6, stem: 3223, fault:25. flip_cnt: 1, stem_cnt: 94, fault_cnt:52 +[UP] flip: 9, stem: 1616, fault:25. flip_cnt: 4, stem_cnt: 93, fault_cnt:49 +[UP] flip: 52, stem: 1611, fault:25. flip_cnt: 9, stem_cnt: 93, fault_cnt:49 +[UP] flip: 0, stem: 3224, fault:25. flip_cnt: 0, stem_cnt: 95, fault_cnt:90 +[UP] flip: 18, stem: 3220, fault:25. flip_cnt: 2, stem_cnt: 94, fault_cnt:88 +[UP] flip: 16, stem: 1610, fault:25. flip_cnt: 2, stem_cnt: 94, fault_cnt:88 +[UP] flip: 13, stem: 1610, fault:25. flip_cnt: 2, stem_cnt: 94, fault_cnt:88 +[UP] flip: 22, stem: 1610, fault:25. flip_cnt: 2, stem_cnt: 94, fault_cnt:88 +[UP] flip: 22, stem: 1623, fault:25. flip_cnt: 2, stem_cnt: 93, fault_cnt:55 +[UP] flip: 6, stem: 2, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:61 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 4881, fault:3. flip_cnt: 3, stem_cnt: 84, fault_cnt:55 +[UP] flip: 8, stem: 4874, fault:9. flip_cnt: 3, stem_cnt: 93, fault_cnt:46 +[UP] flip: 3, stem: 8128, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:37 +[UP] flip: 12, stem: 4884, fault:19. flip_cnt: 3, stem_cnt: 86, fault_cnt:48 +[UP] flip: 0, stem: 1625, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:57 +[UP] flip: 0, stem: 1626, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:57 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 9789, fault:3. flip_cnt: 9, stem_cnt: 87, fault_cnt:69 +[UP] flip: 9, stem: 8160, fault:9. flip_cnt: 4, stem_cnt: 91, fault_cnt:46 +[UP] flip: 8, stem: 1634, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:54 +[UP] flip: 12, stem: 0, fault:20. flip_cnt: 3, stem_cnt: 96, fault_cnt:53 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 13089, fault:3. flip_cnt: 7, stem_cnt: 87, fault_cnt:48 +[UP] flip: 38, stem: 4912, fault:9. flip_cnt: 15, stem_cnt: 92, fault_cnt:40 +[UP] flip: 43, stem: 6549, fault:20. flip_cnt: 15, stem_cnt: 93, fault_cnt:45 +[UP] flip: 11, stem: 4914, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:63 +[UP] flip: 15, stem: 1641, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:58 +[UP] flip: 12, stem: 3281, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:60 +[UP] flip: 243, stem: 2, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11509, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:20 +[UP] flip: 0, stem: 1646, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:24 +[UP] flip: 0, stem: 1647, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:21 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8241, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:24 +[UP] flip: 31, stem: 1, fault:9. flip_cnt: 13, stem_cnt: 95, fault_cnt:30 +[UP] flip: 0, stem: 1651, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:34 +[UP] flip: 0, stem: 3300, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:34 +[UP] flip: 30, stem: 4955, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 4963, fault:3. flip_cnt: 3, stem_cnt: 92, fault_cnt:28 +[UP] flip: 22, stem: 3311, fault:9. flip_cnt: 11, stem_cnt: 93, fault_cnt:29 +[UP] flip: 13, stem: 6625, fault:20. flip_cnt: 4, stem_cnt: 91, fault_cnt:36 +[UP] flip: 0, stem: 1658, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:50 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 4981, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:37 +[UP] flip: 9, stem: 1670, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:57 +[UP] flip: 15, stem: 1664, fault:23. flip_cnt: 4, stem_cnt: 93, fault_cnt:39 +[UP] flip: 126, stem: 1665, fault:23. flip_cnt: 37, stem_cnt: 93, fault_cnt:34 +[UP] flip: 29, stem: 3, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 7, stem: 3332, fault:23. flip_cnt: 1, stem_cnt: 92, fault_cnt:64 +[UP] flip: 77, stem: 1668, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:78 +[UP] flip: 16, stem: 1668, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:90 +[UP] flip: 18, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:93 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 11692, fault:3. flip_cnt: 9, stem_cnt: 87, fault_cnt:28 +[UP] flip: 3, stem: 1673, fault:9. flip_cnt: 1, stem_cnt: 93, fault_cnt:18 +[UP] flip: 25, stem: 5013, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:20 +[UP] flip: 0, stem: 5020, fault:19. flip_cnt: 0, stem_cnt: 92, fault_cnt:25 +[UP] flip: 0, stem: 3347, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:25 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 22, stem: 6704, fault:3. flip_cnt: 11, stem_cnt: 92, fault_cnt:15 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 6715, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:17 +[UP] flip: 16, stem: 5034, fault:10. flip_cnt: 7, stem_cnt: 94, fault_cnt:37 +[UP] flip: 21, stem: 3356, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:35 +[UP] flip: 15, stem: 1678, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 14, stem: 1678, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 12, stem: 1678, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 13, stem: 1678, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 11, stem: 1678, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 20, stem: 1678, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 19, stem: 1678, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 21, stem: 1678, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 88, stem: 1681, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:47 +[UP] flip: 10, stem: 3332, fault:23. flip_cnt: 1, stem_cnt: 94, fault_cnt:50 +[UP] flip: 10, stem: 3370, fault:23. flip_cnt: 1, stem_cnt: 94, fault_cnt:81 +[UP] flip: 27, stem: 1693, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:80 +[UP] flip: 83, stem: 3, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:74 +[UP] flip: 15, stem: 8391, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:82 +[UP] flip: 20, stem: 1684, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:111 +[UP] flip: 7, stem: 1684, fault:19. flip_cnt: 1, stem_cnt: 95, fault_cnt:111 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 1, stem: 8494, fault:3. flip_cnt: 1, stem_cnt: 87, fault_cnt:26 +[UP] flip: 0, stem: 8496, fault:10. flip_cnt: 0, stem_cnt: 90, fault_cnt:30 +[UP] flip: 24, stem: 1700, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:56 +[UP] flip: 10, stem: 8499, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:54 +[UP] flip: 0, stem: 1699, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:51 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 10, stem: 8523, fault:3. flip_cnt: 9, stem_cnt: 88, fault_cnt:40 +[UP] flip: 8, stem: 1714, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:42 +[UP] flip: 78, stem: 6826, fault:20. flip_cnt: 23, stem_cnt: 90, fault_cnt:26 +[UP] flip: 10, stem: 3413, fault:19. flip_cnt: 2, stem_cnt: 93, fault_cnt:44 +[UP] flip: 16, stem: 5124, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:50 +[UP] flip: 0, stem: 3415, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:51 +[UP] flip: 44, stem: 1710, fault:19. flip_cnt: 7, stem_cnt: 95, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 9, stem: 7, fault:0. flip_cnt: 9, stem_cnt: 89, fault_cnt:36 +[UP] flip: 5, stem: 6861, fault:3. flip_cnt: 3, stem_cnt: 83, fault_cnt:35 +[UP] flip: 0, stem: 5143, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:44 +[UP] flip: 0, stem: 1716, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 6870, fault:3. flip_cnt: 11, stem_cnt: 90, fault_cnt:18 +[UP] flip: 6, stem: 5157, fault:9. flip_cnt: 3, stem_cnt: 88, fault_cnt:55 +[UP] flip: 8, stem: 3436, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:43 +[UP] flip: 15, stem: 3438, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 10, stem: 5166, fault:3. flip_cnt: 7, stem_cnt: 93, fault_cnt:78 +[UP] flip: 21, stem: 6891, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:83 +[UP] flip: 108, stem: 10346, fault:20. flip_cnt: 37, stem_cnt: 88, fault_cnt:17 +[UP] flip: 3, stem: 6896, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:11 +[UP] flip: 0, stem: 8624, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:21 +[UP] flip: 0, stem: 6905, fault:19. flip_cnt: 0, stem_cnt: 92, fault_cnt:21 +[UP] flip: 0, stem: 1723, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:21 +[UP] flip: 0, stem: 1722, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:21 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 13849, fault:3. flip_cnt: 0, stem_cnt: 87, fault_cnt:22 +[UP] flip: 0, stem: 1733, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:46 +[UP] flip: 73, stem: 1736, fault:20. flip_cnt: 23, stem_cnt: 92, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 5208, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:67 +[UP] flip: 6, stem: 3481, fault:9. flip_cnt: 3, stem_cnt: 85, fault_cnt:67 +[UP] flip: 8, stem: 6949, fault:20. flip_cnt: 3, stem_cnt: 91, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 12174, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:42 +[UP] flip: 7, stem: 0, fault:9. flip_cnt: 3, stem_cnt: 96, fault_cnt:72 +[UP] flip: 4, stem: 1742, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:74 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 1745, fault:3. flip_cnt: 9, stem_cnt: 93, fault_cnt:41 +[UP] flip: 3, stem: 1, fault:9. flip_cnt: 1, stem_cnt: 95, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 8738, fault:3. flip_cnt: 3, stem_cnt: 83, fault_cnt:33 +[UP] flip: 17, stem: 6987, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:37 +[UP] flip: 9, stem: 1754, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:48 +[UP] flip: 11, stem: 1746, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 16, stem: 1751, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:34 +[UP] flip: 41, stem: 2, fault:20. flip_cnt: 9, stem_cnt: 94, fault_cnt:33 +[UP] flip: 15, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:44 +[UP] flip: 94, stem: 1, fault:20. flip_cnt: 12, stem_cnt: 95, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8776, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:25 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:25 +[UP] flip: 0, stem: 3514, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:22 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:25 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3521, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 5289, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:31 +[UP] flip: 20, stem: 3526, fault:9. flip_cnt: 9, stem_cnt: 93, fault_cnt:49 +[UP] flip: 0, stem: 7057, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:44 +[UP] flip: 9, stem: 3529, fault:24. flip_cnt: 3, stem_cnt: 94, fault_cnt:51 +[UP] flip: 0, stem: 3533, fault:24. flip_cnt: 0, stem_cnt: 93, fault_cnt:38 +[UP] flip: 44, stem: 1766, fault:24. flip_cnt: 7, stem_cnt: 95, fault_cnt:44 +[UP] flip: 50, stem: 1766, fault:24. flip_cnt: 7, stem_cnt: 95, fault_cnt:43 +[UP] flip: 233, stem: 1763, fault:24. flip_cnt: 37, stem_cnt: 94, fault_cnt:37 +[UP] flip: 7, stem: 3526, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:58 +[UP] flip: 22, stem: 1, fault:30. flip_cnt: 3, stem_cnt: 95, fault_cnt:56 +[UP] flip: 70, stem: 3530, fault:30. flip_cnt: 9, stem_cnt: 93, fault_cnt:55 +[UP] flip: 12, stem: 5291, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:93 +[UP] flip: 0, stem: 5323, fault:19. flip_cnt: 0, stem_cnt: 92, fault_cnt:105 +[UP] flip: 0, stem: 1776, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:82 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8886, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:37 +[UP] flip: 21, stem: 7113, fault:10. flip_cnt: 9, stem_cnt: 90, fault_cnt:37 +[UP] flip: 8, stem: 3557, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:59 +[UP] flip: 143, stem: 2, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:46 +[UP] flip: 0, stem: 2, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:49 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 22, stem: 5350, fault:3. flip_cnt: 12, stem_cnt: 92, fault_cnt:52 +[UP] flip: 3, stem: 5353, fault:9. flip_cnt: 1, stem_cnt: 92, fault_cnt:25 +[UP] flip: 88, stem: 5354, fault:20. flip_cnt: 31, stem_cnt: 93, fault_cnt:29 +[UP] flip: 29, stem: 3568, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:23 +[UP] flip: 32, stem: 8932, fault:20. flip_cnt: 7, stem_cnt: 91, fault_cnt:34 +[UP] flip: 0, stem: 5363, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 1793, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:70 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 5377, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:49 +[UP] flip: 0, stem: 7173, fault:9. flip_cnt: 0, stem_cnt: 91, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 7182, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:26 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 10, stem: 7189, fault:3. flip_cnt: 5, stem_cnt: 91, fault_cnt:41 +[UP] flip: 0, stem: 3603, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:36 +[UP] flip: 10, stem: 8994, fault:20. flip_cnt: 3, stem_cnt: 91, fault_cnt:41 +[UP] flip: 0, stem: 8997, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 7209, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:27 +[UP] flip: 0, stem: 1802, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:27 +[UP] flip: 0, stem: 1804, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:37 +[UP] flip: 8, stem: 1807, fault:24. flip_cnt: 2, stem_cnt: 93, fault_cnt:46 +[UP] flip: 22, stem: 1, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:49 +[UP] flip: 19, stem: 2, fault:24. flip_cnt: 4, stem_cnt: 94, fault_cnt:41 +[UP] flip: 22, stem: 1809, fault:24. flip_cnt: 3, stem_cnt: 94, fault_cnt:39 +[UP] flip: 45, stem: 1809, fault:24. flip_cnt: 7, stem_cnt: 94, fault_cnt:40 +[UP] flip: 52, stem: 3618, fault:24. flip_cnt: 7, stem_cnt: 94, fault_cnt:41 +[UP] flip: 27, stem: 1810, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 25, stem: 1810, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 32, stem: 1810, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 29, stem: 1810, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 52, stem: 1810, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:56 +[UP] flip: 23, stem: 1810, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 30, stem: 1810, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 132, stem: 1812, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:52 +[UP] flip: 18, stem: 1804, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:83 +[UP] flip: 31, stem: 2, fault:39. flip_cnt: 2, stem_cnt: 94, fault_cnt:83 +[UP] flip: 101, stem: 3, fault:39. flip_cnt: 9, stem_cnt: 93, fault_cnt:78 +[UP] flip: 18, stem: 5432, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:84 +[UP] flip: 18, stem: 5439, fault:20. flip_cnt: 1, stem_cnt: 86, fault_cnt:82 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 10953, fault:3. flip_cnt: 9, stem_cnt: 87, fault_cnt:17 +[UP] flip: 0, stem: 3653, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:49 +[UP] flip: 8, stem: 1833, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:45 +[UP] flip: 0, stem: 3657, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:43 +[UP] flip: 21, stem: 1829, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 9158, fault:3. flip_cnt: 9, stem_cnt: 88, fault_cnt:25 +[UP] flip: 19, stem: 14655, fault:9. flip_cnt: 7, stem_cnt: 88, fault_cnt:37 +[UP] flip: 26, stem: 1832, fault:23. flip_cnt: 9, stem_cnt: 94, fault_cnt:52 +[UP] flip: 15, stem: 9164, fault:23. flip_cnt: 3, stem_cnt: 87, fault_cnt:50 +[UP] flip: 18, stem: 9164, fault:23. flip_cnt: 3, stem_cnt: 87, fault_cnt:50 +[UP] flip: 19, stem: 1832, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 45, stem: 1832, fault:23. flip_cnt: 7, stem_cnt: 94, fault_cnt:37 +[UP] flip: 64, stem: 2, fault:20. flip_cnt: 8, stem_cnt: 94, fault_cnt:42 +[UP] flip: 0, stem: 3672, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 3683, fault:3. flip_cnt: 1, stem_cnt: 93, fault_cnt:41 +[UP] flip: 19, stem: 1843, fault:10. flip_cnt: 9, stem_cnt: 93, fault_cnt:46 +[UP] flip: 11, stem: 1849, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:44 +[UP] flip: 0, stem: 5533, fault:19. flip_cnt: 0, stem_cnt: 92, fault_cnt:43 +[UP] flip: 0, stem: 3689, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 3694, fault:3. flip_cnt: 7, stem_cnt: 94, fault_cnt:19 +[UP] flip: 0, stem: 1849, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:27 +[UP] flip: 0, stem: 1850, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:18 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:24 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 9262, fault:3. flip_cnt: 1, stem_cnt: 89, fault_cnt:47 +[UP] flip: 18, stem: 1854, fault:10. flip_cnt: 9, stem_cnt: 93, fault_cnt:91 +[UP] flip: 9, stem: 1860, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:90 +[UP] flip: 9, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:66 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11143, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:33 +[UP] flip: 22, stem: 3, fault:9. flip_cnt: 8, stem_cnt: 93, fault_cnt:33 +[UP] flip: 0, stem: 1, fault:11. flip_cnt: 0, stem_cnt: 95, fault_cnt:54 +[UP] flip: 2, stem: 5576, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:50 +[UP] flip: 14, stem: 1, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 45, stem: 3, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:44 +[UP] flip: 11, stem: 0, fault:19. flip_cnt: 2, stem_cnt: 96, fault_cnt:91 +[UP] flip: 16, stem: 0, fault:19. flip_cnt: 3, stem_cnt: 96, fault_cnt:91 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 5599, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:44 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 7474, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:14 +[UP] flip: 19, stem: 9344, fault:9. flip_cnt: 7, stem_cnt: 91, fault_cnt:50 +[UP] flip: 30, stem: 1871, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:43 +[UP] flip: 44, stem: 1868, fault:24. flip_cnt: 10, stem_cnt: 95, fault_cnt:40 +[UP] flip: 131, stem: 1872, fault:20. flip_cnt: 28, stem_cnt: 93, fault_cnt:32 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 9378, fault:3. flip_cnt: 9, stem_cnt: 88, fault_cnt:13 +[UP] flip: 17, stem: 5627, fault:9. flip_cnt: 7, stem_cnt: 93, fault_cnt:27 +[UP] flip: 22, stem: 2, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:39 +[UP] flip: 12, stem: 3763, fault:20. flip_cnt: 3, stem_cnt: 85, fault_cnt:43 +[UP] flip: 15, stem: 1883, fault:19. flip_cnt: 3, stem_cnt: 88, fault_cnt:47 +[UP] flip: 60, stem: 1, fault:19. flip_cnt: 11, stem_cnt: 95, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 5648, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:18 +[UP] flip: 0, stem: 5650, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:19 +[UP] flip: 125, stem: 9418, fault:20. flip_cnt: 37, stem_cnt: 91, fault_cnt:15 +[UP] flip: 45, stem: 9420, fault:19. flip_cnt: 11, stem_cnt: 92, fault_cnt:28 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 3775, fault:3. flip_cnt: 3, stem_cnt: 93, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 13223, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:55 +[UP] flip: 4, stem: 5671, fault:9. flip_cnt: 2, stem_cnt: 92, fault_cnt:36 +[UP] flip: 0, stem: 1892, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:41 +[UP] flip: 11, stem: 3782, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 0, stem: 5674, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:35 +[UP] flip: 12, stem: 7568, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:42 +[UP] flip: 14, stem: 11357, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:18 +[UP] flip: 0, stem: 11356, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:35 +[UP] flip: 0, stem: 13253, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:37 +[UP] flip: 0, stem: 15149, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:35 +[UP] flip: 11, stem: 20828, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:28 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 7605, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:33 +[UP] flip: 23, stem: 1905, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:38 +[UP] flip: 6, stem: 3807, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:66 +[UP] flip: 17, stem: 5709, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:70 +[UP] flip: 10, stem: 1906, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:39 +[UP] flip: 10, stem: 1907, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:33 +[UP] flip: 121, stem: 3813, fault:19. flip_cnt: 19, stem_cnt: 94, fault_cnt:37 +[UP] flip: 23, stem: 0, fault:19. flip_cnt: 3, stem_cnt: 96, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 22, stem: 1913, fault:3. flip_cnt: 11, stem_cnt: 92, fault_cnt:38 +[UP] flip: 21, stem: 1911, fault:9. flip_cnt: 7, stem_cnt: 95, fault_cnt:45 +[UP] flip: 0, stem: 1, fault:11. flip_cnt: 0, stem_cnt: 95, fault_cnt:41 +[UP] flip: 0, stem: 1915, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:41 +[UP] flip: 0, stem: 3827, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:41 +[UP] flip: 79, stem: 3823, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 7677, fault:3. flip_cnt: 0, stem_cnt: 83, fault_cnt:33 +[UP] flip: 22, stem: 3839, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:38 +[UP] flip: 3, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:71 +[UP] flip: 3, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:71 +[UP] flip: 12, stem: 1919, fault:25. flip_cnt: 2, stem_cnt: 94, fault_cnt:72 +[UP] flip: 27, stem: 1919, fault:25. flip_cnt: 9, stem_cnt: 93, fault_cnt:67 +[UP] flip: 0, stem: 3849, fault:25. flip_cnt: 0, stem_cnt: 86, fault_cnt:78 +[UP] flip: 114, stem: 3844, fault:20. flip_cnt: 15, stem_cnt: 92, fault_cnt:97 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 3855, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:45 +[UP] flip: 9, stem: 1936, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:45 +[UP] flip: 14, stem: 3858, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:31 +[UP] flip: 0, stem: 5786, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:30 +[UP] flip: 27, stem: 0, fault:20. flip_cnt: 7, stem_cnt: 96, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 3864, fault:3. flip_cnt: 3, stem_cnt: 94, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 1937, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:39 +[UP] flip: 0, stem: 1944, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:36 +[UP] flip: 8, stem: 7744, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:46 +[UP] flip: 0, stem: 9682, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:48 +[UP] flip: 10, stem: 3873, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:50 +[UP] flip: 184, stem: 2, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 13588, fault:3. flip_cnt: 2, stem_cnt: 88, fault_cnt:70 +[UP] flip: 0, stem: 9711, fault:9. flip_cnt: 0, stem_cnt: 90, fault_cnt:60 +[UP] flip: 133, stem: 1945, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:16 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 7781, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:51 +[UP] flip: 2, stem: 1, fault:9. flip_cnt: 1, stem_cnt: 95, fault_cnt:49 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1949, fault:3. flip_cnt: 0, stem_cnt: 94, fault_cnt:49 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 3901, fault:3. flip_cnt: 3, stem_cnt: 93, fault_cnt:49 +[UP] flip: 8, stem: 1952, fault:9. flip_cnt: 3, stem_cnt: 94, fault_cnt:46 +[UP] flip: 0, stem: 1953, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:58 +[UP] flip: 0, stem: 3904, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:58 +[UP] flip: 0, stem: 5857, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:58 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 46, stem: 7825, fault:3. flip_cnt: 23, stem_cnt: 91, fault_cnt:47 +[UP] flip: 9, stem: 5872, fault:9. flip_cnt: 3, stem_cnt: 92, fault_cnt:74 +[UP] flip: 0, stem: 3915, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:70 +[UP] flip: 70, stem: 1, fault:20. flip_cnt: 15, stem_cnt: 95, fault_cnt:62 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 7845, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:76 +[UP] flip: 11, stem: 1963, fault:9. flip_cnt: 4, stem_cnt: 94, fault_cnt:59 +[UP] flip: 17, stem: 3925, fault:18. flip_cnt: 5, stem_cnt: 94, fault_cnt:58 +[UP] flip: 31, stem: 1966, fault:18. flip_cnt: 7, stem_cnt: 93, fault_cnt:43 +[UP] flip: 45, stem: 3928, fault:25. flip_cnt: 9, stem_cnt: 92, fault_cnt:48 +[UP] flip: 7, stem: 1964, fault:25. flip_cnt: 1, stem_cnt: 95, fault_cnt:95 +[UP] flip: 15, stem: 1963, fault:25. flip_cnt: 2, stem_cnt: 94, fault_cnt:93 +[UP] flip: 51, stem: 1963, fault:25. flip_cnt: 9, stem_cnt: 93, fault_cnt:88 +[UP] flip: 8, stem: 5896, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:97 +[UP] flip: 10, stem: 7865, fault:20. flip_cnt: 2, stem_cnt: 91, fault_cnt:98 +[UP] flip: 251, stem: 13790, fault:20. flip_cnt: 27, stem_cnt: 87, fault_cnt:98 +[UP] flip: 12, stem: 7886, fault:20. flip_cnt: 2, stem_cnt: 91, fault_cnt:67 +[UP] flip: 116, stem: 2, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:86 +[UP] flip: 0, stem: 1975, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:90 +[UP] flip: 47, stem: 3946, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:93 +[UP] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 7913, fault:3. flip_cnt: 2, stem_cnt: 91, fault_cnt:37 +[UP] flip: 11, stem: 3960, fault:9. flip_cnt: 4, stem_cnt: 92, fault_cnt:30 +[UP] flip: 23, stem: 3963, fault:23. flip_cnt: 9, stem_cnt: 91, fault_cnt:33 +[UP] flip: 17, stem: 5940, fault:23. flip_cnt: 5, stem_cnt: 93, fault_cnt:64 +[UP] flip: 25, stem: 5940, fault:25. flip_cnt: 5, stem_cnt: 94, fault_cnt:72 +[UP] flip: 4, stem: 5947, fault:25. flip_cnt: 1, stem_cnt: 86, fault_cnt:75 +[UP] flip: 13, stem: 5950, fault:25. flip_cnt: 3, stem_cnt: 94, fault_cnt:90 +[UP] flip: 30, stem: 1978, fault:25. flip_cnt: 4, stem_cnt: 95, fault_cnt:91 +[UP] flip: 22, stem: 1978, fault:25. flip_cnt: 3, stem_cnt: 95, fault_cnt:91 +[UP] flip: 27, stem: 1978, fault:25. flip_cnt: 3, stem_cnt: 95, fault_cnt:91 +[UP] flip: 17, stem: 1992, fault:20. flip_cnt: 2, stem_cnt: 91, fault_cnt:100 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9953, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:26 +[UP] flip: 48, stem: 2, fault:9. flip_cnt: 23, stem_cnt: 94, fault_cnt:16 +[UP] flip: 8, stem: 1994, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:27 +[UP] flip: 55, stem: 5978, fault:20. flip_cnt: 15, stem_cnt: 92, fault_cnt:30 +[UP] flip: 45, stem: 5979, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:34 +[UP] flip: 23, stem: 1990, fault:26. flip_cnt: 5, stem_cnt: 95, fault_cnt:52 +[UP] flip: 22, stem: 1996, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:43 +[UP] flip: 25, stem: 3993, fault:26. flip_cnt: 3, stem_cnt: 94, fault_cnt:39 +[UP] flip: 72, stem: 3, fault:26. flip_cnt: 9, stem_cnt: 93, fault_cnt:52 +[UP] flip: 8, stem: 3999, fault:26. flip_cnt: 1, stem_cnt: 93, fault_cnt:88 +[UP] flip: 9, stem: 5995, fault:26. flip_cnt: 1, stem_cnt: 92, fault_cnt:56 +[UP] flip: 21, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:92 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 2005, fault:3. flip_cnt: 9, stem_cnt: 93, fault_cnt:50 +[UP] flip: 9, stem: 2006, fault:9. flip_cnt: 4, stem_cnt: 93, fault_cnt:47 +[UP] flip: 0, stem: 8021, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:49 +[UP] flip: 9, stem: 0, fault:20. flip_cnt: 3, stem_cnt: 96, fault_cnt:59 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6026, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:35 +[UP] flip: 0, stem: 2018, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:42 +[UP] flip: 5, stem: 14070, fault:20. flip_cnt: 2, stem_cnt: 87, fault_cnt:32 +[UP] flip: 0, stem: 12065, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:42 +[UP] flip: 0, stem: 8046, fault:19. flip_cnt: 0, stem_cnt: 92, fault_cnt:42 +[UP] flip: 0, stem: 2014, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6046, fault:4. flip_cnt: 0, stem_cnt: 92, fault_cnt:63 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 6053, fault:3. flip_cnt: 4, stem_cnt: 91, fault_cnt:40 +[UP] flip: 77, stem: 4038, fault:9. flip_cnt: 37, stem_cnt: 92, fault_cnt:38 +[UP] flip: 30, stem: 4039, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:41 +[UP] flip: 4, stem: 6058, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:53 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 2023, fault:3. flip_cnt: 0, stem_cnt: 94, fault_cnt:17 +[UP] flip: 21, stem: 1, fault:9. flip_cnt: 7, stem_cnt: 95, fault_cnt:37 +[UP] flip: 7, stem: 2024, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 2027, fault:3. flip_cnt: 4, stem_cnt: 94, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 1, stem: 8114, fault:3. flip_cnt: 1, stem_cnt: 90, fault_cnt:21 +[UP] flip: 15, stem: 8115, fault:9. flip_cnt: 7, stem_cnt: 92, fault_cnt:40 +[UP] flip: 6, stem: 10150, fault:20. flip_cnt: 3, stem_cnt: 86, fault_cnt:37 +[UP] flip: 9, stem: 2029, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 188, stem: 2029, fault:24. flip_cnt: 37, stem_cnt: 94, fault_cnt:37 +[UP] flip: 5, stem: 2029, fault:24. flip_cnt: 1, stem_cnt: 94, fault_cnt:57 +[UP] flip: 19, stem: 2034, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:56 +[UP] flip: 21, stem: 1, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 71, stem: 3, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:52 +[UP] flip: 9, stem: 6101, fault:24. flip_cnt: 1, stem_cnt: 91, fault_cnt:64 +[UP] flip: 4, stem: 8152, fault:24. flip_cnt: 2, stem_cnt: 92, fault_cnt:88 +[UP] flip: 20, stem: 4068, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:91 +[UP] flip: 17, stem: 2027, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:84 +[UP] flip: 25, stem: 2027, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:86 +[UP] flip: 27, stem: 2027, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:85 +[UP] flip: 91, stem: 2017, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:81 +[UP] flip: 30, stem: 8134, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:94 +[UP] flip: 16, stem: 10157, fault:20. flip_cnt: 1, stem_cnt: 87, fault_cnt:91 +[UP] flip: 25, stem: 2033, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:74 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 8193, fault:3. flip_cnt: 2, stem_cnt: 91, fault_cnt:65 +[UP] flip: 2, stem: 2050, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:70 +[UP] flip: 7, stem: 2052, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:79 +[UP] flip: 0, stem: 2052, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:90 +[UP] flip: 9, stem: 2053, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 14387, fault:3. flip_cnt: 3, stem_cnt: 80, fault_cnt:58 +[UP] flip: 38, stem: 8221, fault:10. flip_cnt: 15, stem_cnt: 91, fault_cnt:75 +[UP] flip: 0, stem: 2057, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:97 +[UP] flip: 30, stem: 0, fault:19. flip_cnt: 7, stem_cnt: 96, fault_cnt:94 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 4120, fault:3. flip_cnt: 1, stem_cnt: 92, fault_cnt:19 +[UP] flip: 0, stem: 2062, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:27 +[UP] flip: 0, stem: 12367, fault:20. flip_cnt: 0, stem_cnt: 89, fault_cnt:24 +[UP] flip: 0, stem: 12369, fault:20. flip_cnt: 0, stem_cnt: 87, fault_cnt:24 +[UP] flip: 0, stem: 12369, fault:20. flip_cnt: 0, stem_cnt: 87, fault_cnt:24 +[UP] flip: 0, stem: 6184, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:23 +[UP] flip: 48, stem: 6181, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:15 +[UP] flip: 0, stem: 16493, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:23 +[UP] flip: 0, stem: 4128, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:24 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 10345, fault:3. flip_cnt: 1, stem_cnt: 91, fault_cnt:26 +[UP] flip: 92, stem: 8280, fault:10. flip_cnt: 37, stem_cnt: 91, fault_cnt:34 +[UP] flip: 100, stem: 2074, fault:17. flip_cnt: 27, stem_cnt: 92, fault_cnt:64 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 4147, fault:3. flip_cnt: 2, stem_cnt: 93, fault_cnt:23 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 10376, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:48 +[UP] flip: 38, stem: 2079, fault:10. flip_cnt: 20, stem_cnt: 92, fault_cnt:41 +[UP] flip: 17, stem: 2076, fault:22. flip_cnt: 5, stem_cnt: 95, fault_cnt:58 +[UP] flip: 10, stem: 2076, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 14, stem: 2076, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 14, stem: 2076, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 16, stem: 2076, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 23, stem: 2076, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 28, stem: 2076, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 28, stem: 2076, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 94, stem: 2077, fault:22. flip_cnt: 9, stem_cnt: 93, fault_cnt:46 +[UP] flip: 11, stem: 4163, fault:19. flip_cnt: 1, stem_cnt: 93, fault_cnt:83 +[UP] flip: 0, stem: 2088, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:85 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 10446, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:30 +[UP] flip: 2, stem: 3, fault:9. flip_cnt: 1, stem_cnt: 93, fault_cnt:11 +[UP] flip: 35, stem: 2, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:17 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6280, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:48 +[UP] flip: 24, stem: 4189, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:47 +[UP] flip: 0, stem: 4191, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:56 +[UP] flip: 10, stem: 4190, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:49 +[UP] flip: 138, stem: 6293, fault:19. flip_cnt: 27, stem_cnt: 91, fault_cnt:48 +[UP] flip: 4, stem: 1, fault:19. flip_cnt: 1, stem_cnt: 95, fault_cnt:36 +[UP] flip: 249, stem: 2, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:35 +[UP] flip: 0, stem: 2096, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8409, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:58 +[UP] flip: 9, stem: 4215, fault:9. flip_cnt: 3, stem_cnt: 85, fault_cnt:50 +[UP] flip: 59, stem: 6313, fault:20. flip_cnt: 19, stem_cnt: 92, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6319, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:32 +[UP] flip: 21, stem: 4215, fault:9. flip_cnt: 7, stem_cnt: 93, fault_cnt:35 +[UP] flip: 7, stem: 8430, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:23 +[UP] flip: 0, stem: 4217, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:39 +[UP] flip: 0, stem: 8436, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:39 +[UP] flip: 0, stem: 4221, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:42 +[UP] flip: 58, stem: 6334, fault:19. flip_cnt: 9, stem_cnt: 92, fault_cnt:35 +[UP] flip: 0, stem: 6336, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:37 +[UP] flip: 118, stem: 4218, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:38 +[UP] flip: 142, stem: 2108, fault:19. flip_cnt: 19, stem_cnt: 93, fault_cnt:39 +[UP] flip: 117, stem: 2110, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 8474, fault:3. flip_cnt: 8, stem_cnt: 90, fault_cnt:87 +[UP] flip: 25, stem: 6357, fault:10. flip_cnt: 9, stem_cnt: 92, fault_cnt:92 +[UP] flip: 7, stem: 4241, fault:19. flip_cnt: 2, stem_cnt: 93, fault_cnt:70 +[UP] flip: 146, stem: 2119, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:44 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 4250, fault:3. flip_cnt: 8, stem_cnt: 90, fault_cnt:10 +[UP] flip: 20, stem: 6373, fault:10. flip_cnt: 7, stem_cnt: 92, fault_cnt:44 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 12757, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:29 +[UP] flip: 17, stem: 6382, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:55 +[UP] flip: 9, stem: 4262, fault:20. flip_cnt: 3, stem_cnt: 86, fault_cnt:47 +[UP] flip: 16, stem: 2, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:37 +[UP] flip: 16, stem: 4256, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 6397, fault:3. flip_cnt: 4, stem_cnt: 92, fault_cnt:54 +[UP] flip: 10, stem: 2136, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:51 +[UP] flip: 37, stem: 6403, fault:20. flip_cnt: 10, stem_cnt: 92, fault_cnt:33 +[UP] flip: 7, stem: 8539, fault:20. flip_cnt: 2, stem_cnt: 91, fault_cnt:40 +[UP] flip: 35, stem: 1, fault:20. flip_cnt: 7, stem_cnt: 95, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 12829, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:41 +[UP] flip: 0, stem: 2148, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:58 +[UP] flip: 0, stem: 8561, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:41 +[UP] flip: 12, stem: 2141, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 13, stem: 1, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 51, stem: 2140, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:47 +[UP] flip: 7, stem: 1, fault:24. flip_cnt: 1, stem_cnt: 95, fault_cnt:85 +[UP] flip: 191, stem: 2143, fault:20. flip_cnt: 27, stem_cnt: 92, fault_cnt:71 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8589, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:76 +[UP] flip: 0, stem: 4303, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:34 +[UP] flip: 12, stem: 4299, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:46 +[UP] flip: 26, stem: 1, fault:20. flip_cnt: 7, stem_cnt: 95, fault_cnt:32 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 10761, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:19 +[UP] flip: 28, stem: 12919, fault:9. flip_cnt: 11, stem_cnt: 89, fault_cnt:14 +[UP] flip: 24, stem: 4307, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:30 +[UP] flip: 0, stem: 15077, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:30 +[UP] flip: 0, stem: 17232, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:30 +[UP] flip: 0, stem: 2158, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:50 +[UP] flip: 24, stem: 0, fault:19. flip_cnt: 4, stem_cnt: 96, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6481, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:31 +[UP] flip: 21, stem: 8645, fault:9. flip_cnt: 7, stem_cnt: 91, fault_cnt:36 +[UP] flip: 13, stem: 4326, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:20 +[UP] flip: 0, stem: 4327, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:22 +[UP] flip: 34, stem: 0, fault:19. flip_cnt: 7, stem_cnt: 96, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 6501, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:39 +[UP] flip: 7, stem: 2176, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:38 +[UP] flip: 0, stem: 6505, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:37 +[UP] flip: 0, stem: 2168, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:24 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8685, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:38 +[UP] flip: 46, stem: 2174, fault:9. flip_cnt: 19, stem_cnt: 93, fault_cnt:35 +[UP] flip: 26, stem: 6516, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:52 +[UP] flip: 40, stem: 6522, fault:19. flip_cnt: 11, stem_cnt: 92, fault_cnt:39 +[UP] flip: 15, stem: 2174, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 215, stem: 2172, fault:20. flip_cnt: 37, stem_cnt: 94, fault_cnt:46 +[UP] flip: 0, stem: 2178, fault:27. flip_cnt: 0, stem_cnt: 94, fault_cnt:65 +[UP] flip: 23, stem: 1, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 71, stem: 2173, fault:27. flip_cnt: 9, stem_cnt: 93, fault_cnt:52 +[UP] flip: 9, stem: 6532, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:65 +[UP] flip: 0, stem: 6536, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:102 +[UP] flip: 3, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:100 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 2186, fault:3. flip_cnt: 7, stem_cnt: 93, fault_cnt:19 +[UP] flip: 83, stem: 2187, fault:9. flip_cnt: 37, stem_cnt: 93, fault_cnt:30 +[UP] flip: 12, stem: 4373, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:44 +[UP] flip: 29, stem: 4372, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:29 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6569, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:38 +[UP] flip: 0, stem: 6571, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:34 +[UP] flip: 54, stem: 2193, fault:20. flip_cnt: 23, stem_cnt: 93, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 21, stem: 8773, fault:3. flip_cnt: 11, stem_cnt: 91, fault_cnt:25 +[UP] flip: 0, stem: 2203, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:43 +[UP] flip: 33, stem: 6585, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:39 +[UP] flip: 175, stem: 2198, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:46 +[UP] flip: 90, stem: 2196, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:55 +[UP] flip: 46, stem: 2, fault:19. flip_cnt: 9, stem_cnt: 94, fault_cnt:55 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 11006, fault:3. flip_cnt: 4, stem_cnt: 90, fault_cnt:41 +[UP] flip: 25, stem: 6607, fault:9. flip_cnt: 10, stem_cnt: 92, fault_cnt:34 +[UP] flip: 102, stem: 2205, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:22 +[UP] flip: 0, stem: 2205, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 13237, fault:3. flip_cnt: 7, stem_cnt: 89, fault_cnt:48 +[UP] flip: 0, stem: 2208, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:60 +[UP] flip: 0, stem: 2209, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:63 +[UP] flip: 0, stem: 2208, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:57 +[UP] flip: 36, stem: 1, fault:20. flip_cnt: 7, stem_cnt: 95, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 15484, fault:3. flip_cnt: 11, stem_cnt: 89, fault_cnt:50 +[UP] flip: 32, stem: 1, fault:10. flip_cnt: 16, stem_cnt: 95, fault_cnt:55 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 8863, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:74 +[UP] flip: 2, stem: 8865, fault:9. flip_cnt: 1, stem_cnt: 91, fault_cnt:55 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 8875, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:55 +[UP] flip: 0, stem: 2220, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:42 +[UP] flip: 56, stem: 2221, fault:20. flip_cnt: 23, stem_cnt: 94, fault_cnt:43 +[UP] flip: 10, stem: 6660, fault:24. flip_cnt: 3, stem_cnt: 93, fault_cnt:47 +[UP] flip: 37, stem: 4444, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:48 +[UP] flip: 16, stem: 2218, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 20, stem: 2218, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 22, stem: 2218, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 15, stem: 2218, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 20, stem: 2218, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 25, stem: 2218, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 10, stem: 2220, fault:26. flip_cnt: 1, stem_cnt: 95, fault_cnt:84 +[UP] flip: 39, stem: 2231, fault:33. flip_cnt: 5, stem_cnt: 94, fault_cnt:76 +[UP] flip: 378, stem: 4462, fault:33. flip_cnt: 37, stem_cnt: 93, fault_cnt:44 +[UP] flip: 15, stem: 4440, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:76 +[UP] flip: 10, stem: 2219, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:90 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 11176, fault:3. flip_cnt: 8, stem_cnt: 90, fault_cnt:30 +[UP] flip: 53, stem: 1, fault:9. flip_cnt: 23, stem_cnt: 95, fault_cnt:42 +[UP] flip: 11, stem: 4475, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:53 +[UP] flip: 15, stem: 6711, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:50 +[UP] flip: 0, stem: 8955, fault:20. flip_cnt: 0, stem_cnt: 88, fault_cnt:59 +[UP] flip: 0, stem: 8951, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:54 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11219, fault:3. flip_cnt: 0, stem_cnt: 82, fault_cnt:30 +[UP] flip: 22, stem: 6732, fault:9. flip_cnt: 9, stem_cnt: 90, fault_cnt:32 +[UP] flip: 7, stem: 2243, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:75 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 2248, fault:3. flip_cnt: 7, stem_cnt: 93, fault_cnt:30 +[UP] flip: 11, stem: 4497, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:26 +[UP] flip: 9, stem: 2257, fault:20. flip_cnt: 3, stem_cnt: 86, fault_cnt:39 +[UP] flip: 8, stem: 4500, fault:24. flip_cnt: 2, stem_cnt: 92, fault_cnt:40 +[UP] flip: 41, stem: 2, fault:24. flip_cnt: 9, stem_cnt: 94, fault_cnt:34 +[UP] flip: 9, stem: 2250, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:48 +[UP] flip: 101, stem: 2249, fault:20. flip_cnt: 15, stem_cnt: 94, fault_cnt:59 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6763, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:20 +[UP] flip: 3, stem: 2, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:31 +[UP] flip: 62, stem: 2258, fault:20. flip_cnt: 23, stem_cnt: 93, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 6775, fault:3. flip_cnt: 3, stem_cnt: 92, fault_cnt:40 +[UP] flip: 22, stem: 2262, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:61 +[UP] flip: 3, stem: 2264, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:85 +[UP] flip: 151, stem: 2263, fault:24. flip_cnt: 37, stem_cnt: 93, fault_cnt:79 +[UP] flip: 1, stem: 2266, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:73 +[UP] flip: 117, stem: 2, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:81 +[UP] flip: 59, stem: 2266, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:76 +[UP] flip: 36, stem: 1, fault:20. flip_cnt: 5, stem_cnt: 95, fault_cnt:79 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 15870, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:47 +[UP] flip: 0, stem: 2269, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:33 +[UP] flip: 3, stem: 6804, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 29, stem: 9086, fault:3. flip_cnt: 15, stem_cnt: 90, fault_cnt:12 +[UP] flip: 16, stem: 2276, fault:9. flip_cnt: 8, stem_cnt: 91, fault_cnt:23 +[UP] flip: 9, stem: 2272, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 5, stem: 2274, fault:23. flip_cnt: 2, stem_cnt: 95, fault_cnt:47 +[UP] flip: 14, stem: 2274, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 16, stem: 2272, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 17, stem: 2272, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 18, stem: 2272, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 45, stem: 2272, fault:23. flip_cnt: 5, stem_cnt: 95, fault_cnt:50 +[UP] flip: 22, stem: 2272, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 28, stem: 2272, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +[UP] flip: 20, stem: 2, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:87 +[UP] flip: 91, stem: 3, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:82 +[UP] flip: 9, stem: 6841, fault:23. flip_cnt: 1, stem_cnt: 86, fault_cnt:91 +[UP] flip: 29, stem: 2285, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:87 +[UP] flip: 28, stem: 2285, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:87 +[UP] flip: 9, stem: 2284, fault:23. flip_cnt: 2, stem_cnt: 95, fault_cnt:82 +[UP] flip: 25, stem: 2285, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:87 +[UP] flip: 33, stem: 2285, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:86 +[UP] flip: 39, stem: 4559, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:84 +[UP] flip: 31, stem: 2285, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:84 +[UP] flip: 153, stem: 4571, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:79 +[UP] flip: 14, stem: 9137, fault:39. flip_cnt: 1, stem_cnt: 86, fault_cnt:97 +[UP] flip: 36, stem: 6842, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:122 +[UP] flip: 344, stem: 2297, fault:20. flip_cnt: 15, stem_cnt: 94, fault_cnt:117 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 66, stem: 9194, fault:3. flip_cnt: 37, stem_cnt: 90, fault_cnt:14 +[UP] flip: 19, stem: 4601, fault:12. flip_cnt: 9, stem_cnt: 91, fault_cnt:59 +[UP] flip: 3, stem: 6898, fault:18. flip_cnt: 1, stem_cnt: 93, fault_cnt:67 +[UP] flip: 80, stem: 2300, fault:18. flip_cnt: 19, stem_cnt: 94, fault_cnt:107 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11516, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:75 +[UP] flip: 0, stem: 4609, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:67 +[UP] flip: 0, stem: 2305, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:41 +[UP] flip: 0, stem: 4610, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:41 +[UP] flip: 58, stem: 6918, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:38 +[UP] flip: 13, stem: 4617, fault:19. flip_cnt: 2, stem_cnt: 93, fault_cnt:39 +[UP] flip: 12, stem: 4612, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:43 +[UP] flip: 79, stem: 4618, fault:19. flip_cnt: 11, stem_cnt: 94, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 9251, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:39 +[UP] flip: 9, stem: 4635, fault:9. flip_cnt: 3, stem_cnt: 85, fault_cnt:61 +[UP] flip: 22, stem: 13884, fault:20. flip_cnt: 9, stem_cnt: 88, fault_cnt:42 +[UP] flip: 34, stem: 4627, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:40 +[UP] flip: 17, stem: 9256, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:31 +[UP] flip: 0, stem: 9258, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:38 +[UP] flip: 0, stem: 2314, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:41 +[UP] flip: 31, stem: 2312, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:44 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11606, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:38 +[UP] flip: 5, stem: 9, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:36 +[UP] flip: 0, stem: 6970, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:31 +[UP] flip: 10, stem: 2323, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 179, stem: 4647, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:33 +[UP] flip: 58, stem: 3, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:50 +[UP] flip: 8, stem: 4652, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:51 +[UP] flip: 159, stem: 4654, fault:20. flip_cnt: 27, stem_cnt: 91, fault_cnt:70 +[UP] flip: 12, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:73 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 11656, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:30 +[UP] flip: 21, stem: 4665, fault:9. flip_cnt: 7, stem_cnt: 93, fault_cnt:61 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 11672, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:28 +[UP] flip: 4, stem: 7005, fault:9. flip_cnt: 2, stem_cnt: 92, fault_cnt:26 +[UP] flip: 11, stem: 7007, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:32 +[UP] flip: 12, stem: 2335, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 17, stem: 2335, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 16, stem: 2335, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 0, stem: 2340, fault:24. flip_cnt: 0, stem_cnt: 95, fault_cnt:86 +[UP] flip: 14, stem: 0, fault:20. flip_cnt: 2, stem_cnt: 96, fault_cnt:92 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 2346, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:47 +[UP] flip: 6, stem: 2353, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:55 +[UP] flip: 10, stem: 4691, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:32 +[UP] flip: 12, stem: 1, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 43, stem: 3, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:48 +[UP] flip: 11, stem: 2349, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:56 +[UP] flip: 3, stem: 2, fault:24. flip_cnt: 1, stem_cnt: 94, fault_cnt:86 +[UP] flip: 194, stem: 4698, fault:20. flip_cnt: 27, stem_cnt: 91, fault_cnt:72 +[UP] flip: 16, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:75 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11766, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:59 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11776, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:45 +[UP] flip: 23, stem: 4713, fault:10. flip_cnt: 8, stem_cnt: 93, fault_cnt:51 +[UP] flip: 12, stem: 2358, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:67 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 10, fault:0. flip_cnt: 3, stem_cnt: 86, fault_cnt:35 +[UP] flip: 12, stem: 7081, fault:3. flip_cnt: 7, stem_cnt: 92, fault_cnt:21 +[UP] flip: 0, stem: 4723, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:23 +[UP] flip: 28, stem: 2362, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:39 +[UP] flip: 5, stem: 4723, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:35 +[UP] flip: 0, stem: 11821, fault:20. flip_cnt: 0, stem_cnt: 90, fault_cnt:31 +[UP] flip: 7, stem: 4729, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:25 +[UP] flip: 74, stem: 1, fault:19. flip_cnt: 13, stem_cnt: 95, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 9473, fault:3. flip_cnt: 2, stem_cnt: 91, fault_cnt:27 +[UP] flip: 0, stem: 4738, fault:10. flip_cnt: 0, stem_cnt: 94, fault_cnt:47 +[UP] flip: 10, stem: 2369, fault:21. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 14, stem: 2369, fault:21. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 12, stem: 2369, fault:21. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 19, stem: 2369, fault:21. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 21, stem: 2369, fault:21. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 18, stem: 2369, fault:21. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 21, stem: 2369, fault:21. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 24, stem: 2369, fault:21. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 11, stem: 4, fault:21. flip_cnt: 1, stem_cnt: 92, fault_cnt:89 +[UP] flip: 81, stem: 5, fault:18. flip_cnt: 8, stem_cnt: 91, fault_cnt:83 +[UP] flip: 174, stem: 4762, fault:19. flip_cnt: 15, stem_cnt: 92, fault_cnt:82 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11911, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:34 +[UP] flip: 7, stem: 8, fault:9. flip_cnt: 3, stem_cnt: 88, fault_cnt:60 +[UP] flip: 0, stem: 4767, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:33 +[UP] flip: 0, stem: 4769, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:32 +[UP] flip: 0, stem: 7153, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:33 +[UP] flip: 0, stem: 9541, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:33 +[UP] flip: 15, stem: 11927, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 14341, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:37 +[UP] flip: 0, stem: 4784, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:53 +[UP] flip: 0, stem: 4785, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:42 +[UP] flip: 15, stem: 1, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 76, stem: 1, fault:19. flip_cnt: 13, stem_cnt: 95, fault_cnt:33 +[UP] flip: 202, stem: 2391, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:19 +[UP] flip: 0, stem: 2391, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 4798, fault:3. flip_cnt: 4, stem_cnt: 92, fault_cnt:16 +[UP] flip: 0, stem: 7204, fault:9. flip_cnt: 0, stem_cnt: 85, fault_cnt:29 +[UP] flip: 0, stem: 2401, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:38 +[UP] flip: 0, stem: 7200, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:25 +[UP] flip: 36, stem: 9603, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:28 +[UP] flip: 0, stem: 9604, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:25 +[UP] flip: 0, stem: 14411, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:24 +[UP] flip: 0, stem: 19220, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:24 +[UP] flip: 0, stem: 24029, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:24 +[UP] flip: 0, stem: 14415, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 12047, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:33 +[UP] flip: 7, stem: 2411, fault:9. flip_cnt: 3, stem_cnt: 94, fault_cnt:48 +[UP] flip: 24, stem: 2414, fault:20. flip_cnt: 7, stem_cnt: 92, fault_cnt:42 +[UP] flip: 36, stem: 2, fault:19. flip_cnt: 9, stem_cnt: 94, fault_cnt:54 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9657, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:18 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:36 +[UP] flip: 0, stem: 2417, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:27 +[UP] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 12096, fault:3. flip_cnt: 4, stem_cnt: 90, fault_cnt:68 +[UP] flip: 3, stem: 7261, fault:10. flip_cnt: 1, stem_cnt: 92, fault_cnt:57 +[UP] flip: 8, stem: 4848, fault:19. flip_cnt: 3, stem_cnt: 86, fault_cnt:56 +[UP] flip: 10, stem: 2424, fault:19. flip_cnt: 2, stem_cnt: 93, fault_cnt:54 +[UP] flip: 18, stem: 2419, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 17, stem: 2419, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 16, stem: 2419, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 24, stem: 2419, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 27, stem: 2419, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 23, stem: 2419, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 31, stem: 2419, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 35, stem: 2419, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 38, stem: 2419, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 110, stem: 2422, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:43 +[UP] flip: 14, stem: 4841, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:79 +[UP] flip: 522, stem: 2420, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:52 +[UP] flip: 5, stem: 4841, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:79 +[UP] flip: 33, stem: 4855, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:82 +[UP] flip: 28, stem: 2420, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:78 +[UP] flip: 35, stem: 2420, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:78 +[UP] flip: 37, stem: 2420, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:79 +[UP] flip: 37, stem: 2420, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:77 +[UP] flip: 13, stem: 2420, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:78 +[UP] flip: 147, stem: 4820, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:74 +[UP] flip: 21, stem: 7261, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:83 +[UP] flip: 22, stem: 4848, fault:19. flip_cnt: 1, stem_cnt: 87, fault_cnt:81 +[UP] flip: 38, stem: 2423, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:103 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9789, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:41 +[UP] flip: 9, stem: 2449, fault:9. flip_cnt: 3, stem_cnt: 94, fault_cnt:31 +[UP] flip: 26, stem: 7348, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:26 +[UP] flip: 6, stem: 2451, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:65 +[UP] flip: 129, stem: 4900, fault:19. flip_cnt: 27, stem_cnt: 94, fault_cnt:53 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 20, stem: 2454, fault:3. flip_cnt: 11, stem_cnt: 94, fault_cnt:34 +[UP] flip: 8, stem: 2463, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:40 +[UP] flip: 0, stem: 9821, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:28 +[UP] flip: 0, stem: 2455, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 7375, fault:3. flip_cnt: 2, stem_cnt: 92, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 19681, fault:3. flip_cnt: 0, stem_cnt: 87, fault_cnt:36 +[UP] flip: 0, stem: 4922, fault:10. flip_cnt: 0, stem_cnt: 94, fault_cnt:29 +[UP] flip: 28, stem: 2, fault:18. flip_cnt: 8, stem_cnt: 94, fault_cnt:43 +[UP] flip: 65, stem: 2, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 17256, fault:3. flip_cnt: 8, stem_cnt: 88, fault_cnt:53 +[UP] flip: 0, stem: 2467, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:64 +[UP] flip: 23, stem: 7401, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:64 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 9879, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:51 +[UP] flip: 11, stem: 4941, fault:10. flip_cnt: 4, stem_cnt: 93, fault_cnt:49 +[UP] flip: 38, stem: 4944, fault:19. flip_cnt: 12, stem_cnt: 92, fault_cnt:35 +[UP] flip: 47, stem: 1, fault:19. flip_cnt: 10, stem_cnt: 95, fault_cnt:39 +[UP] flip: 17, stem: 4947, fault:19. flip_cnt: 3, stem_cnt: 93, fault_cnt:33 +[UP] flip: 0, stem: 7421, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 4955, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:72 +[UP] flip: 33, stem: 7432, fault:9. flip_cnt: 11, stem_cnt: 92, fault_cnt:52 +[UP] flip: 132, stem: 2480, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:38 +[UP] flip: 0, stem: 4957, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 12406, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:52 +[UP] flip: 0, stem: 9927, fault:10. flip_cnt: 0, stem_cnt: 92, fault_cnt:35 +[UP] flip: 8, stem: 7453, fault:19. flip_cnt: 3, stem_cnt: 86, fault_cnt:45 +[UP] flip: 0, stem: 4966, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:49 +[UP] flip: 92, stem: 2, fault:19. flip_cnt: 23, stem_cnt: 94, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 4975, fault:3. flip_cnt: 4, stem_cnt: 93, fault_cnt:27 +[UP] flip: 20, stem: 2488, fault:9. flip_cnt: 9, stem_cnt: 94, fault_cnt:30 +[UP] flip: 26, stem: 9957, fault:20. flip_cnt: 7, stem_cnt: 91, fault_cnt:37 +[UP] flip: 10, stem: 4982, fault:24. flip_cnt: 2, stem_cnt: 92, fault_cnt:52 +[UP] flip: 111, stem: 2491, fault:20. flip_cnt: 27, stem_cnt: 93, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 39, stem: 4986, fault:3. flip_cnt: 24, stem_cnt: 94, fault_cnt:46 +[UP] flip: 97, stem: 2, fault:9. flip_cnt: 37, stem_cnt: 94, fault_cnt:52 +[UP] flip: 8, stem: 2505, fault:20. flip_cnt: 3, stem_cnt: 85, fault_cnt:54 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 4997, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:22 +[UP] flip: 0, stem: 9993, fault:9. flip_cnt: 0, stem_cnt: 91, fault_cnt:23 +[UP] flip: 0, stem: 4997, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:18 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 10005, fault:3. flip_cnt: 3, stem_cnt: 91, fault_cnt:38 +[UP] flip: 0, stem: 2511, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:47 +[UP] flip: 0, stem: 10013, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:49 +[UP] flip: 0, stem: 7511, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:54 +[UP] flip: 0, stem: 10018, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:49 +[UP] flip: 11, stem: 5011, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:49 +[UP] flip: 65, stem: 2501, fault:20. flip_cnt: 11, stem_cnt: 95, fault_cnt:57 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 10037, fault:3. flip_cnt: 2, stem_cnt: 91, fault_cnt:47 +[UP] flip: 21, stem: 5021, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:36 +[UP] flip: 0, stem: 12553, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:31 +[UP] flip: 0, stem: 7538, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:30 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:44 +[UP] flip: 18, stem: 0, fault:19. flip_cnt: 3, stem_cnt: 96, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 10065, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:16 +[UP] flip: 0, stem: 2516, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:21 +[UP] flip: 0, stem: 5035, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:18 +[UP] flip: 0, stem: 5036, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:18 +[UP] flip: 0, stem: 7558, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:18 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 15133, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:38 +[UP] flip: 0, stem: 9, fault:9. flip_cnt: 0, stem_cnt: 87, fault_cnt:58 +[UP] flip: 0, stem: 10097, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:53 +[UP] flip: 10, stem: 12622, fault:20. flip_cnt: 2, stem_cnt: 92, fault_cnt:53 +[UP] flip: 36, stem: 12624, fault:20. flip_cnt: 9, stem_cnt: 90, fault_cnt:39 +[UP] flip: 6, stem: 2528, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:59 +[UP] flip: 64, stem: 1, fault:19. flip_cnt: 9, stem_cnt: 95, fault_cnt:82 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 12651, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:41 +[UP] flip: 23, stem: 5061, fault:10. flip_cnt: 9, stem_cnt: 93, fault_cnt:26 +[UP] flip: 24, stem: 10129, fault:19. flip_cnt: 7, stem_cnt: 91, fault_cnt:35 +[UP] flip: 0, stem: 12664, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:25 +[UP] flip: 0, stem: 12664, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:25 +[UP] flip: 0, stem: 5067, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 10151, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:34 +[UP] flip: 50, stem: 5078, fault:9. flip_cnt: 19, stem_cnt: 92, fault_cnt:27 +[UP] flip: 11, stem: 10153, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:42 +[UP] flip: 12, stem: 2538, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 9, stem: 2538, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 13, stem: 2538, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 12, stem: 2538, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 8, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:81 +[UP] flip: 154, stem: 2540, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:70 +[UP] flip: 75, stem: 2548, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:76 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 2551, fault:3. flip_cnt: 9, stem_cnt: 93, fault_cnt:59 +[UP] flip: 8, stem: 5101, fault:9. flip_cnt: 3, stem_cnt: 93, fault_cnt:52 +[UP] flip: 63, stem: 2553, fault:20. flip_cnt: 19, stem_cnt: 93, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 17874, fault:3. flip_cnt: 9, stem_cnt: 86, fault_cnt:44 +[UP] flip: 0, stem: 7664, fault:9. flip_cnt: 0, stem_cnt: 89, fault_cnt:48 +[UP] flip: 0, stem: 7663, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:43 +[UP] flip: 27, stem: 5113, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:36 +[UP] flip: 0, stem: 2558, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:36 +[UP] flip: 9, stem: 2557, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:25 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 12801, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:25 +[UP] flip: 9, stem: 2563, fault:12. flip_cnt: 4, stem_cnt: 93, fault_cnt:37 +[UP] flip: 8, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:58 +[UP] flip: 111, stem: 4, fault:20. flip_cnt: 28, stem_cnt: 92, fault_cnt:42 +[UP] flip: 0, stem: 2565, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:38 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +[UP] flip: 26, stem: 1, fault:19. flip_cnt: 4, stem_cnt: 95, fault_cnt:44 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 7705, fault:3. flip_cnt: 7, stem_cnt: 92, fault_cnt:57 +[UP] flip: 110, stem: 2571, fault:9. flip_cnt: 37, stem_cnt: 93, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 10285, fault:3. flip_cnt: 3, stem_cnt: 91, fault_cnt:26 +[UP] flip: 0, stem: 2581, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:53 +[UP] flip: 9, stem: 2572, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 13, stem: 2572, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 14, stem: 2572, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 18, stem: 2572, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 21, stem: 2572, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 23, stem: 2572, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 28, stem: 2572, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 26, stem: 2572, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 19, stem: 2, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:89 +[UP] flip: 19, stem: 2, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:89 +[UP] flip: 226, stem: 2584, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:81 +[UP] flip: 0, stem: 2585, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:82 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 7759, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:34 +[UP] flip: 15, stem: 2596, fault:9. flip_cnt: 7, stem_cnt: 86, fault_cnt:47 +[UP] flip: 18, stem: 7765, fault:20. flip_cnt: 5, stem_cnt: 92, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 12951, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:61 +[UP] flip: 11, stem: 7773, fault:9. flip_cnt: 4, stem_cnt: 93, fault_cnt:55 +[UP] flip: 0, stem: 12959, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:44 +[UP] flip: 20, stem: 7776, fault:19. flip_cnt: 5, stem_cnt: 94, fault_cnt:56 +[UP] flip: 18, stem: 10369, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:51 +[UP] flip: 17, stem: 7776, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:63 +[UP] flip: 17, stem: 12961, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:63 +[UP] flip: 19, stem: 7786, fault:19. flip_cnt: 3, stem_cnt: 93, fault_cnt:40 +[UP] flip: 17, stem: 5195, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:43 +[UP] flip: 29, stem: 7787, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 13006, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:41 +[UP] flip: 3, stem: 5205, fault:9. flip_cnt: 1, stem_cnt: 93, fault_cnt:55 +[UP] flip: 41, stem: 1, fault:20. flip_cnt: 15, stem_cnt: 95, fault_cnt:41 +[UP] flip: 27, stem: 2602, fault:24. flip_cnt: 7, stem_cnt: 94, fault_cnt:38 +[UP] flip: 182, stem: 2607, fault:24. flip_cnt: 37, stem_cnt: 93, fault_cnt:33 +[UP] flip: 17, stem: 2601, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 17, stem: 2601, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 13, stem: 2601, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 21, stem: 2601, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 23, stem: 2601, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 41, stem: 2601, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:58 +[UP] flip: 104, stem: 2604, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:54 +[UP] flip: 8, stem: 5218, fault:24. flip_cnt: 1, stem_cnt: 94, fault_cnt:58 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 13075, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:18 +[UP] flip: 17, stem: 7849, fault:9. flip_cnt: 7, stem_cnt: 92, fault_cnt:31 +[UP] flip: 13, stem: 5234, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:26 +[UP] flip: 14, stem: 10470, fault:20. flip_cnt: 4, stem_cnt: 91, fault_cnt:31 +[UP] flip: 21, stem: 5234, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 7864, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 10493, fault:3. flip_cnt: 4, stem_cnt: 91, fault_cnt:17 +[UP] flip: 8, stem: 5257, fault:9. flip_cnt: 3, stem_cnt: 85, fault_cnt:78 +[UP] flip: 35, stem: 5250, fault:20. flip_cnt: 15, stem_cnt: 94, fault_cnt:73 +[UP] flip: 12, stem: 2625, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:87 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 15769, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:69 +[UP] flip: 9, stem: 3, fault:9. flip_cnt: 3, stem_cnt: 93, fault_cnt:64 +[UP] flip: 62, stem: 1, fault:20. flip_cnt: 19, stem_cnt: 95, fault_cnt:73 +[UP] flip: 80, stem: 2631, fault:20. flip_cnt: 19, stem_cnt: 95, fault_cnt:73 +[UP] flip: 12, stem: 7895, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:68 +[UP] flip: 118, stem: 2636, fault:20. flip_cnt: 20, stem_cnt: 92, fault_cnt:58 +[UP] flip: 27, stem: 5262, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:64 +[UP] flip: 32, stem: 2628, fault:19. flip_cnt: 4, stem_cnt: 95, fault_cnt:66 +[UP] flip: 21, stem: 2628, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:66 +[UP] flip: 23, stem: 2628, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:66 +[UP] flip: 24, stem: 2628, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:66 +[UP] flip: 32, stem: 2628, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:66 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 5283, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:47 +[UP] flip: 7, stem: 2651, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:51 +[UP] flip: 10, stem: 2644, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:53 +[UP] flip: 0, stem: 5287, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:52 +[UP] flip: 72, stem: 1, fault:20. flip_cnt: 13, stem_cnt: 95, fault_cnt:34 +[UP] flip: 233, stem: 2, fault:20. flip_cnt: 37, stem_cnt: 94, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 19, stem: 2650, fault:3. flip_cnt: 11, stem_cnt: 93, fault_cnt:64 +[UP] flip: 0, stem: 5297, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:66 +[UP] flip: 2, stem: 2, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:58 +[UP] flip: 34, stem: 5301, fault:20. flip_cnt: 8, stem_cnt: 93, fault_cnt:56 +[UP] flip: 49, stem: 7958, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:45 +[UP] flip: 6, stem: 2652, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:53 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 2657, fault:3. flip_cnt: 4, stem_cnt: 93, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 13286, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:21 +[UP] flip: 19, stem: 7973, fault:9. flip_cnt: 7, stem_cnt: 93, fault_cnt:28 +[UP] flip: 0, stem: 2660, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 13305, fault:3. flip_cnt: 7, stem_cnt: 91, fault_cnt:37 +[UP] flip: 27, stem: 3, fault:10. flip_cnt: 11, stem_cnt: 93, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 15985, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:20 +[UP] flip: 2, stem: 1, fault:10. flip_cnt: 1, stem_cnt: 95, fault_cnt:25 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 21337, fault:3. flip_cnt: 9, stem_cnt: 87, fault_cnt:34 +[UP] flip: 0, stem: 5337, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:40 +[UP] flip: 0, stem: 8004, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:11 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 8016, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:41 +[UP] flip: 3, stem: 5345, fault:10. flip_cnt: 1, stem_cnt: 93, fault_cnt:21 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 41, stem: 5350, fault:3. flip_cnt: 23, stem_cnt: 92, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 11, stem: 10706, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:51 +[UP] flip: 7, stem: 2684, fault:12. flip_cnt: 3, stem_cnt: 88, fault_cnt:61 +[UP] flip: 10, stem: 1, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 13, stem: 1, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 51, stem: 3, fault:22. flip_cnt: 9, stem_cnt: 93, fault_cnt:47 +[UP] flip: 12, stem: 2682, fault:22. flip_cnt: 2, stem_cnt: 94, fault_cnt:63 +[UP] flip: 5, stem: 3, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:91 +[UP] flip: 181, stem: 5369, fault:20. flip_cnt: 27, stem_cnt: 91, fault_cnt:80 +[UP] flip: 225, stem: 5365, fault:20. flip_cnt: 27, stem_cnt: 93, fault_cnt:70 +[UP] flip: 245, stem: 0, fault:19. flip_cnt: 27, stem_cnt: 96, fault_cnt:69 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8062, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:22 +[UP] flip: 0, stem: 2687, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:22 +[UP] flip: 0, stem: 2690, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:18 +[UP] flip: 0, stem: 2691, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:26 +[UP] flip: 0, stem: 8075, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:25 +[UP] flip: 41, stem: 5381, fault:20. flip_cnt: 9, stem_cnt: 94, fault_cnt:24 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 8085, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:74 +[UP] flip: 7, stem: 13475, fault:9. flip_cnt: 3, stem_cnt: 91, fault_cnt:44 +[UP] flip: 22, stem: 2695, fault:20. flip_cnt: 9, stem_cnt: 94, fault_cnt:50 +[UP] flip: 11, stem: 8091, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:49 +[UP] flip: 0, stem: 10789, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:49 +[UP] flip: 24, stem: 1, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:28 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 5405, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:32 +[UP] flip: 0, stem: 2711, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:40 +[UP] flip: 11, stem: 10811, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:38 +[UP] flip: 0, stem: 10819, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:42 +[UP] flip: 4, stem: 5408, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:53 +[UP] flip: 30, stem: 5408, fault:20. flip_cnt: 5, stem_cnt: 94, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 16249, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:70 +[UP] flip: 29, stem: 8126, fault:9. flip_cnt: 10, stem_cnt: 93, fault_cnt:44 +[UP] flip: 4, stem: 5421, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:15 +[UP] flip: 75, stem: 2715, fault:19. flip_cnt: 19, stem_cnt: 91, fault_cnt:15 +[UP] flip: 26, stem: 2, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:36 +[UP] flip: 74, stem: 1, fault:19. flip_cnt: 15, stem_cnt: 95, fault_cnt:32 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 69, stem: 13576, fault:3. flip_cnt: 37, stem_cnt: 90, fault_cnt:23 +[UP] flip: 2, stem: 2718, fault:9. flip_cnt: 1, stem_cnt: 93, fault_cnt:41 +[UP] flip: 14, stem: 8151, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 66, stem: 19035, fault:3. flip_cnt: 37, stem_cnt: 87, fault_cnt:24 +[UP] flip: 14, stem: 1, fault:9. flip_cnt: 5, stem_cnt: 95, fault_cnt:44 +[UP] flip: 0, stem: 2722, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:35 +[UP] flip: 9, stem: 2720, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 5449, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:39 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:40 +[UP] flip: 68, stem: 2729, fault:20. flip_cnt: 18, stem_cnt: 92, fault_cnt:28 +[UP] flip: 75, stem: 5453, fault:20. flip_cnt: 18, stem_cnt: 94, fault_cnt:27 +[UP] flip: 38, stem: 8181, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:46 +[UP] flip: 0, stem: 10908, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 58, stem: 8194, fault:3. flip_cnt: 37, stem_cnt: 92, fault_cnt:27 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 20, stem: 19132, fault:3. flip_cnt: 11, stem_cnt: 88, fault_cnt:57 +[UP] flip: 0, stem: 5469, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:50 +[UP] flip: 0, stem: 8204, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:55 +[UP] flip: 32, stem: 5470, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:57 +[UP] flip: 13, stem: 10939, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:57 +[UP] flip: 18, stem: 8209, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:35 +[UP] flip: 23, stem: 0, fault:20. flip_cnt: 3, stem_cnt: 96, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 10965, fault:3. flip_cnt: 1, stem_cnt: 91, fault_cnt:24 +[UP] flip: 0, stem: 8225, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:27 +[UP] flip: 0, stem: 5487, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:37 +[UP] flip: 18, stem: 0, fault:20. flip_cnt: 4, stem_cnt: 96, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 2747, fault:3. flip_cnt: 0, stem_cnt: 94, fault_cnt:21 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 11, stem: 2750, fault:3. flip_cnt: 9, stem_cnt: 93, fault_cnt:20 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 11002, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:21 +[UP] flip: 0, stem: 9, fault:12. flip_cnt: 0, stem_cnt: 87, fault_cnt:35 +[UP] flip: 20, stem: 5505, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:45 +[UP] flip: 11, stem: 5506, fault:22. flip_cnt: 3, stem_cnt: 94, fault_cnt:36 +[UP] flip: 31, stem: 2754, fault:22. flip_cnt: 7, stem_cnt: 94, fault_cnt:40 +[UP] flip: 37, stem: 5508, fault:22. flip_cnt: 7, stem_cnt: 94, fault_cnt:41 +[UP] flip: 37, stem: 5508, fault:22. flip_cnt: 7, stem_cnt: 94, fault_cnt:42 +[UP] flip: 22, stem: 2755, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:56 +[UP] flip: 30, stem: 2755, fault:22. flip_cnt: 5, stem_cnt: 95, fault_cnt:59 +[UP] flip: 25, stem: 2755, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:56 +[UP] flip: 20, stem: 2755, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:56 +[UP] flip: 28, stem: 2755, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:56 +[UP] flip: 107, stem: 2757, fault:22. flip_cnt: 9, stem_cnt: 93, fault_cnt:55 +[UP] flip: 9, stem: 2, fault:22. flip_cnt: 1, stem_cnt: 94, fault_cnt:57 +[UP] flip: 275, stem: 2, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:62 +[UP] flip: 129, stem: 2767, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:53 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 11073, fault:3. flip_cnt: 11, stem_cnt: 91, fault_cnt:67 +[UP] flip: 0, stem: 5540, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:76 +[UP] flip: 119, stem: 5542, fault:20. flip_cnt: 37, stem_cnt: 92, fault_cnt:14 +[UP] flip: 44, stem: 2, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:23 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 8321, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 11103, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:13 +[UP] flip: 0, stem: 2777, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:35 +[UP] flip: 60, stem: 2779, fault:20. flip_cnt: 19, stem_cnt: 93, fault_cnt:37 +[UP] flip: 157, stem: 2, fault:24. flip_cnt: 37, stem_cnt: 94, fault_cnt:47 +[UP] flip: 3, stem: 2777, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:64 +[UP] flip: 14, stem: 1, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:64 +[UP] flip: 20, stem: 1, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:58 +[UP] flip: 24, stem: 2775, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 42, stem: 2775, fault:26. flip_cnt: 5, stem_cnt: 95, fault_cnt:57 +[UP] flip: 23, stem: 2775, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 27, stem: 2775, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 31, stem: 2775, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 29, stem: 2775, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 23, stem: 2775, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 103, stem: 5553, fault:26. flip_cnt: 9, stem_cnt: 93, fault_cnt:53 +[UP] flip: 16, stem: 8343, fault:26. flip_cnt: 1, stem_cnt: 94, fault_cnt:56 +[UP] flip: 108, stem: 11137, fault:20. flip_cnt: 7, stem_cnt: 92, fault_cnt:50 +[UP] flip: 107, stem: 0, fault:19. flip_cnt: 7, stem_cnt: 96, fault_cnt:69 +[UP] flip: 165, stem: 1, fault:19. flip_cnt: 11, stem_cnt: 95, fault_cnt:66 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 8386, fault:3. flip_cnt: 7, stem_cnt: 92, fault_cnt:30 +[UP] flip: 94, stem: 2798, fault:12. flip_cnt: 37, stem_cnt: 93, fault_cnt:59 +[UP] flip: 4, stem: 1, fault:18. flip_cnt: 1, stem_cnt: 95, fault_cnt:79 +[UP] flip: 7, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:79 +[UP] flip: 0, stem: 2800, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:77 +[UP] flip: 21, stem: 2801, fault:26. flip_cnt: 3, stem_cnt: 94, fault_cnt:70 +[UP] flip: 52, stem: 2797, fault:26. flip_cnt: 9, stem_cnt: 93, fault_cnt:65 +[UP] flip: 19, stem: 5597, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:91 +[UP] flip: 242, stem: 2, fault:20. flip_cnt: 27, stem_cnt: 94, fault_cnt:110 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 16831, fault:3. flip_cnt: 2, stem_cnt: 89, fault_cnt:43 +[UP] flip: 3, stem: 3, fault:9. flip_cnt: 1, stem_cnt: 93, fault_cnt:42 +[UP] flip: 63, stem: 2808, fault:20. flip_cnt: 23, stem_cnt: 94, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 16856, fault:3. flip_cnt: 9, stem_cnt: 88, fault_cnt:50 +[UP] flip: 5, stem: 1, fault:9. flip_cnt: 2, stem_cnt: 95, fault_cnt:43 +[UP] flip: 81, stem: 5621, fault:20. flip_cnt: 23, stem_cnt: 93, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 5628, fault:3. flip_cnt: 2, stem_cnt: 92, fault_cnt:26 +[UP] flip: 10, stem: 2815, fault:9. flip_cnt: 4, stem_cnt: 94, fault_cnt:34 +[UP] flip: 129, stem: 2817, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:23 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 16905, fault:3. flip_cnt: 9, stem_cnt: 87, fault_cnt:28 +[UP] flip: 3, stem: 5638, fault:9. flip_cnt: 1, stem_cnt: 92, fault_cnt:40 +[UP] flip: 11, stem: 8455, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:43 +[UP] flip: 27, stem: 8457, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:44 +[UP] flip: 21, stem: 2818, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 8470, fault:3. flip_cnt: 2, stem_cnt: 92, fault_cnt:69 +[UP] flip: 27, stem: 14121, fault:9. flip_cnt: 9, stem_cnt: 90, fault_cnt:30 +[UP] flip: 99, stem: 5650, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:55 +[UP] flip: 0, stem: 8477, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:58 +[UP] flip: 10, stem: 8482, fault:20. flip_cnt: 2, stem_cnt: 92, fault_cnt:38 +[UP] flip: 14, stem: 2827, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 8493, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:33 +[UP] flip: 18, stem: 9, fault:9. flip_cnt: 9, stem_cnt: 87, fault_cnt:63 +[UP] flip: 7, stem: 8497, fault:20. flip_cnt: 2, stem_cnt: 92, fault_cnt:44 +[UP] flip: 92, stem: 2835, fault:20. flip_cnt: 27, stem_cnt: 92, fault_cnt:58 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 14176, fault:3. flip_cnt: 4, stem_cnt: 90, fault_cnt:56 +[UP] flip: 40, stem: 2, fault:9. flip_cnt: 15, stem_cnt: 94, fault_cnt:70 +[UP] flip: 34, stem: 2839, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:66 +[UP] flip: 18, stem: 1, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:78 +[UP] flip: 22, stem: 1, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:54 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8525, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:38 +[UP] flip: 4, stem: 2, fault:9. flip_cnt: 2, stem_cnt: 94, fault_cnt:34 +[UP] flip: 66, stem: 2, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:44 +[UP] flip: 2, stem: 2846, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:35 +[UP] flip: 22, stem: 5686, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:47 +[UP] flip: 15, stem: 8533, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:41 +[UP] flip: 14, stem: 5688, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:42 +[UP] flip: 41, stem: 5689, fault:27. flip_cnt: 5, stem_cnt: 94, fault_cnt:50 +[UP] flip: 26, stem: 2841, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 25, stem: 2841, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 21, stem: 2841, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 30, stem: 2841, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 36, stem: 2841, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 101, stem: 5684, fault:27. flip_cnt: 9, stem_cnt: 93, fault_cnt:49 +[UP] flip: 14, stem: 8540, fault:27. flip_cnt: 1, stem_cnt: 94, fault_cnt:54 +[UP] flip: 24, stem: 2843, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:97 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:99 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 65, stem: 8579, fault:3. flip_cnt: 37, stem_cnt: 91, fault_cnt:23 +[UP] flip: 1, stem: 2861, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:18 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 11, stem: 8589, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:34 +[UP] flip: 8, stem: 8588, fault:9. flip_cnt: 3, stem_cnt: 93, fault_cnt:35 +[UP] flip: 0, stem: 2865, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:40 +[UP] flip: 0, stem: 2866, fault:24. flip_cnt: 0, stem_cnt: 94, fault_cnt:58 +[UP] flip: 172, stem: 2, fault:24. flip_cnt: 37, stem_cnt: 94, fault_cnt:47 +[UP] flip: 3, stem: 5729, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:73 +[UP] flip: 6, stem: 5729, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:73 +[UP] flip: 7, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:88 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 8614, fault:3. flip_cnt: 4, stem_cnt: 92, fault_cnt:40 +[UP] flip: 47, stem: 5745, fault:9. flip_cnt: 19, stem_cnt: 92, fault_cnt:57 +[UP] flip: 0, stem: 2873, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:54 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:62 +[UP] flip: 24, stem: 0, fault:20. flip_cnt: 4, stem_cnt: 96, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 5755, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:26 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8638, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:56 +[UP] flip: 11, stem: 2880, fault:9. flip_cnt: 4, stem_cnt: 95, fault_cnt:50 +[UP] flip: 44, stem: 2, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:40 +[UP] flip: 0, stem: 5762, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 14423, fault:3. flip_cnt: 9, stem_cnt: 88, fault_cnt:73 +[UP] flip: 8, stem: 11544, fault:9. flip_cnt: 3, stem_cnt: 88, fault_cnt:67 +[UP] flip: 0, stem: 8664, fault:20. flip_cnt: 0, stem_cnt: 85, fault_cnt:39 +[UP] flip: 0, stem: 8660, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:44 +[UP] flip: 14, stem: 0, fault:20. flip_cnt: 3, stem_cnt: 96, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 5789, fault:3. flip_cnt: 3, stem_cnt: 85, fault_cnt:46 +[UP] flip: 8, stem: 8674, fault:9. flip_cnt: 3, stem_cnt: 92, fault_cnt:46 +[UP] flip: 113, stem: 8678, fault:20. flip_cnt: 37, stem_cnt: 91, fault_cnt:28 +[UP] flip: 14, stem: 5785, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:48 +[UP] flip: 4, stem: 8677, fault:19. flip_cnt: 1, stem_cnt: 93, fault_cnt:44 +[UP] flip: 16, stem: 8680, fault:19. flip_cnt: 3, stem_cnt: 93, fault_cnt:47 +[UP] flip: 15, stem: 8682, fault:27. flip_cnt: 3, stem_cnt: 93, fault_cnt:51 +[UP] flip: 16, stem: 5787, fault:27. flip_cnt: 3, stem_cnt: 93, fault_cnt:53 +[UP] flip: 0, stem: 2898, fault:27. flip_cnt: 0, stem_cnt: 93, fault_cnt:61 +[UP] flip: 30, stem: 2890, fault:27. flip_cnt: 5, stem_cnt: 95, fault_cnt:55 +[UP] flip: 16, stem: 2890, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 24, stem: 2890, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 36, stem: 2890, fault:27. flip_cnt: 5, stem_cnt: 95, fault_cnt:54 +[UP] flip: 96, stem: 5786, fault:27. flip_cnt: 9, stem_cnt: 93, fault_cnt:50 +[UP] flip: 12, stem: 23101, fault:27. flip_cnt: 1, stem_cnt: 94, fault_cnt:56 +[UP] flip: 13, stem: 5757, fault:27. flip_cnt: 1, stem_cnt: 94, fault_cnt:90 +[UP] flip: 5, stem: 5757, fault:27. flip_cnt: 1, stem_cnt: 94, fault_cnt:90 +[UP] flip: 29, stem: 5800, fault:27. flip_cnt: 2, stem_cnt: 94, fault_cnt:95 +[UP] flip: 96, stem: 2892, fault:27. flip_cnt: 9, stem_cnt: 93, fault_cnt:85 +[UP] flip: 16, stem: 14485, fault:27. flip_cnt: 1, stem_cnt: 86, fault_cnt:93 +[UP] flip: 64, stem: 28897, fault:27. flip_cnt: 5, stem_cnt: 91, fault_cnt:74 +[UP] flip: 18, stem: 17395, fault:27. flip_cnt: 1, stem_cnt: 85, fault_cnt:105 +[UP] flip: 40, stem: 5798, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:82 +[UP] flip: 33, stem: 2909, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:80 +[UP] flip: 12, stem: 2909, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:82 +[UP] flip: 43, stem: 2909, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:81 +[UP] flip: 40, stem: 5825, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:84 +[UP] flip: 152, stem: 8695, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:77 +[UP] flip: 176, stem: 46204, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:80 +[UP] flip: 229, stem: 49194, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:71 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11685, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:17 +[UP] flip: 16, stem: 5845, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:40 +[UP] flip: 0, stem: 11693, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:35 +[UP] flip: 0, stem: 8771, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:58 +[UP] flip: 55, stem: 2921, fault:20. flip_cnt: 10, stem_cnt: 95, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 11710, fault:3. flip_cnt: 1, stem_cnt: 90, fault_cnt:28 +[UP] flip: 0, stem: 8785, fault:10. flip_cnt: 0, stem_cnt: 92, fault_cnt:40 +[UP] flip: 0, stem: 14642, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:32 +[UP] flip: 58, stem: 2931, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:25 +[UP] flip: 42, stem: 5855, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:25 +[UP] flip: 5, stem: 8789, fault:19. flip_cnt: 1, stem_cnt: 93, fault_cnt:11 +[UP] flip: 0, stem: 20508, fault:19. flip_cnt: 0, stem_cnt: 85, fault_cnt:21 +[UP] flip: 0, stem: 2928, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 62, stem: 8810, fault:3. flip_cnt: 37, stem_cnt: 91, fault_cnt:24 +[UP] flip: 15, stem: 2937, fault:9. flip_cnt: 9, stem_cnt: 94, fault_cnt:44 +[UP] flip: 14, stem: 17629, fault:20. flip_cnt: 4, stem_cnt: 89, fault_cnt:44 +[UP] flip: 18, stem: 17625, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:24 +[UP] flip: 0, stem: 17631, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:48 +[UP] flip: 0, stem: 14698, fault:19. flip_cnt: 0, stem_cnt: 92, fault_cnt:44 +[UP] flip: 44, stem: 5878, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:30 +[UP] flip: 50, stem: 2, fault:19. flip_cnt: 9, stem_cnt: 94, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 17671, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:30 +[UP] flip: 17, stem: 3, fault:9. flip_cnt: 7, stem_cnt: 93, fault_cnt:34 +[UP] flip: 11, stem: 2, fault:23. flip_cnt: 3, stem_cnt: 94, fault_cnt:43 +[UP] flip: 32, stem: 5895, fault:23. flip_cnt: 9, stem_cnt: 92, fault_cnt:42 +[UP] flip: 0, stem: 8854, fault:25. flip_cnt: 0, stem_cnt: 85, fault_cnt:51 +[UP] flip: 200, stem: 5896, fault:25. flip_cnt: 37, stem_cnt: 93, fault_cnt:56 +[UP] flip: 83, stem: 8845, fault:20. flip_cnt: 16, stem_cnt: 92, fault_cnt:61 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 8862, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:66 +[UP] flip: 5, stem: 8863, fault:9. flip_cnt: 2, stem_cnt: 92, fault_cnt:46 +[UP] flip: 13, stem: 8863, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:41 +[UP] flip: 11, stem: 5909, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:43 +[UP] flip: 15, stem: 0, fault:20. flip_cnt: 3, stem_cnt: 96, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 5919, fault:3. flip_cnt: 2, stem_cnt: 93, fault_cnt:36 +[UP] flip: 5, stem: 2959, fault:9. flip_cnt: 2, stem_cnt: 95, fault_cnt:22 +[UP] flip: 0, stem: 2961, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:31 +[UP] flip: 72, stem: 2964, fault:20. flip_cnt: 27, stem_cnt: 92, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 11858, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:20 +[UP] flip: 0, stem: 2966, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:38 +[UP] flip: 10, stem: 5938, fault:20. flip_cnt: 3, stem_cnt: 86, fault_cnt:33 +[UP] flip: 15, stem: 14835, fault:20. flip_cnt: 4, stem_cnt: 90, fault_cnt:20 +[UP] flip: 177, stem: 20769, fault:20. flip_cnt: 37, stem_cnt: 89, fault_cnt:20 +[UP] flip: 25, stem: 5937, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11885, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:41 +[UP] flip: 9, stem: 8915, fault:9. flip_cnt: 3, stem_cnt: 93, fault_cnt:40 +[UP] flip: 5, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:78 +[UP] flip: 61, stem: 2976, fault:20. flip_cnt: 15, stem_cnt: 93, fault_cnt:73 +[UP] flip: 84, stem: 1, fault:19. flip_cnt: 17, stem_cnt: 95, fault_cnt:83 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 11909, fault:3. flip_cnt: 2, stem_cnt: 91, fault_cnt:71 +[UP] flip: 8, stem: 8936, fault:9. flip_cnt: 3, stem_cnt: 91, fault_cnt:45 +[UP] flip: 117, stem: 2981, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:43 +[UP] flip: 0, stem: 5958, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11929, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:77 +[UP] flip: 8, stem: 2992, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:94 +[UP] flip: 7, stem: 2986, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 14931, fault:3. flip_cnt: 3, stem_cnt: 90, fault_cnt:33 +[UP] flip: 22, stem: 8962, fault:10. flip_cnt: 9, stem_cnt: 91, fault_cnt:26 +[UP] flip: 0, stem: 2989, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:54 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 8972, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:38 +[UP] flip: 16, stem: 2995, fault:9. flip_cnt: 7, stem_cnt: 91, fault_cnt:23 +[UP] flip: 116, stem: 2, fault:23. flip_cnt: 37, stem_cnt: 94, fault_cnt:42 +[UP] flip: 10, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:55 +[UP] flip: 14, stem: 1, fault:25. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 52, stem: 2992, fault:25. flip_cnt: 9, stem_cnt: 93, fault_cnt:44 +[UP] flip: 12, stem: 11980, fault:27. flip_cnt: 2, stem_cnt: 92, fault_cnt:60 +[UP] flip: 12, stem: 2998, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:72 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 6002, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:29 +[UP] flip: 44, stem: 3003, fault:9. flip_cnt: 19, stem_cnt: 92, fault_cnt:37 +[UP] flip: 35, stem: 3, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:48 +[UP] flip: 4, stem: 6003, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:64 +[UP] flip: 39, stem: 3005, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:88 +[UP] flip: 81, stem: 3006, fault:20. flip_cnt: 15, stem_cnt: 93, fault_cnt:81 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 15031, fault:3. flip_cnt: 4, stem_cnt: 90, fault_cnt:37 +[UP] flip: 19, stem: 3, fault:12. flip_cnt: 9, stem_cnt: 93, fault_cnt:47 +[UP] flip: 8, stem: 3010, fault:18. flip_cnt: 2, stem_cnt: 93, fault_cnt:54 +[UP] flip: 92, stem: 1, fault:19. flip_cnt: 21, stem_cnt: 95, fault_cnt:70 +[UP] flip: 46, stem: 2, fault:19. flip_cnt: 9, stem_cnt: 94, fault_cnt:66 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 24, stem: 3014, fault:3. flip_cnt: 15, stem_cnt: 93, fault_cnt:34 +[UP] flip: 38, stem: 3014, fault:10. flip_cnt: 15, stem_cnt: 94, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 18090, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:41 +[UP] flip: 20, stem: 3017, fault:9. flip_cnt: 9, stem_cnt: 93, fault_cnt:73 +[UP] flip: 17, stem: 6040, fault:20. flip_cnt: 5, stem_cnt: 86, fault_cnt:66 +[UP] flip: 9, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:49 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 10, stem: 6043, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:37 +[UP] flip: 6, stem: 3028, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:36 +[UP] flip: 9, stem: 12086, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:31 +[UP] flip: 11, stem: 15114, fault:20. flip_cnt: 3, stem_cnt: 86, fault_cnt:33 +[UP] flip: 0, stem: 12089, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:31 +[UP] flip: 0, stem: 12093, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:18 +[UP] flip: 0, stem: 15118, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:17 +[UP] flip: 8, stem: 9064, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:18 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 15154, fault:3. flip_cnt: 3, stem_cnt: 82, fault_cnt:44 +[UP] flip: 0, stem: 15149, fault:9. flip_cnt: 0, stem_cnt: 91, fault_cnt:52 +[UP] flip: 0, stem: 15158, fault:20. flip_cnt: 0, stem_cnt: 85, fault_cnt:58 +[UP] flip: 68, stem: 6065, fault:20. flip_cnt: 15, stem_cnt: 93, fault_cnt:49 +[UP] flip: 76, stem: 3034, fault:20. flip_cnt: 16, stem_cnt: 94, fault_cnt:45 +[UP] flip: 15, stem: 1, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 51, stem: 3031, fault:26. flip_cnt: 9, stem_cnt: 93, fault_cnt:48 +[UP] flip: 16, stem: 6063, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:99 +[UP] flip: 25, stem: 6063, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:99 +[UP] flip: 0, stem: 3030, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:103 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 15203, fault:3. flip_cnt: 9, stem_cnt: 88, fault_cnt:46 +[UP] flip: 0, stem: 3050, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:38 +[UP] flip: 0, stem: 15211, fault:20. flip_cnt: 0, stem_cnt: 90, fault_cnt:28 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 12177, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:44 +[UP] flip: 0, stem: 3046, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:48 +[UP] flip: 0, stem: 15231, fault:20. flip_cnt: 0, stem_cnt: 90, fault_cnt:40 +[UP] flip: 12, stem: 15234, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:50 +[UP] flip: 4, stem: 18286, fault:20. flip_cnt: 2, stem_cnt: 90, fault_cnt:42 +[UP] flip: 94, stem: 3051, fault:20. flip_cnt: 19, stem_cnt: 93, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 21360, fault:3. flip_cnt: 9, stem_cnt: 86, fault_cnt:28 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 18319, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:46 +[UP] flip: 23, stem: 6107, fault:10. flip_cnt: 9, stem_cnt: 93, fault_cnt:42 +[UP] flip: 14, stem: 9163, fault:19. flip_cnt: 4, stem_cnt: 93, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 9175, fault:3. flip_cnt: 7, stem_cnt: 89, fault_cnt:10 +[UP] flip: 0, stem: 3059, fault:10. flip_cnt: 0, stem_cnt: 94, fault_cnt:43 +[UP] flip: 114, stem: 2, fault:22. flip_cnt: 37, stem_cnt: 94, fault_cnt:47 +[UP] flip: 4, stem: 1, fault:22. flip_cnt: 1, stem_cnt: 95, fault_cnt:70 +[UP] flip: 40, stem: 2, fault:19. flip_cnt: 8, stem_cnt: 94, fault_cnt:63 +[UP] flip: 88, stem: 2, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:65 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3065, fault:3. flip_cnt: 0, stem_cnt: 94, fault_cnt:24 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:24 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 15336, fault:3. flip_cnt: 4, stem_cnt: 90, fault_cnt:51 +[UP] flip: 36, stem: 3068, fault:9. flip_cnt: 15, stem_cnt: 94, fault_cnt:73 +[UP] flip: 8, stem: 3071, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:77 +[UP] flip: 8, stem: 2, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:79 +[UP] flip: 46, stem: 3, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:74 +[UP] flip: 6, stem: 3081, fault:20. flip_cnt: 1, stem_cnt: 86, fault_cnt:83 +[UP] flip: 44, stem: 6141, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:63 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 21526, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:26 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 22, stem: 12309, fault:3. flip_cnt: 11, stem_cnt: 91, fault_cnt:73 +[UP] flip: 8, stem: 12311, fault:9. flip_cnt: 3, stem_cnt: 92, fault_cnt:38 +[UP] flip: 4, stem: 3080, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:37 +[UP] flip: 0, stem: 6158, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 15419, fault:3. flip_cnt: 0, stem_cnt: 82, fault_cnt:25 +[UP] flip: 20, stem: 9248, fault:9. flip_cnt: 7, stem_cnt: 93, fault_cnt:34 +[UP] flip: 111, stem: 9251, fault:20. flip_cnt: 37, stem_cnt: 92, fault_cnt:24 +[UP] flip: 30, stem: 12337, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:32 +[UP] flip: 5, stem: 9261, fault:20. flip_cnt: 1, stem_cnt: 90, fault_cnt:47 +[UP] flip: 5, stem: 6176, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:68 +[UP] flip: 88, stem: 9261, fault:20. flip_cnt: 15, stem_cnt: 93, fault_cnt:74 +[UP] flip: 56, stem: 1, fault:20. flip_cnt: 11, stem_cnt: 95, fault_cnt:71 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 9274, fault:3. flip_cnt: 4, stem_cnt: 92, fault_cnt:29 +[UP] flip: 20, stem: 9275, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:48 +[UP] flip: 28, stem: 9280, fault:20. flip_cnt: 7, stem_cnt: 92, fault_cnt:38 +[UP] flip: 13, stem: 3093, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 13, stem: 3093, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 20, stem: 3093, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 21, stem: 3093, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 12, stem: 3093, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 23, stem: 3093, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 20, stem: 3093, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 83, stem: 3093, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:49 +[UP] flip: 11, stem: 6194, fault:24. flip_cnt: 1, stem_cnt: 94, fault_cnt:45 +[UP] flip: 12, stem: 6186, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:39 +[UP] flip: 57, stem: 1, fault:34. flip_cnt: 5, stem_cnt: 95, fault_cnt:58 +[UP] flip: 45, stem: 3092, fault:34. flip_cnt: 4, stem_cnt: 95, fault_cnt:50 +[UP] flip: 3, stem: 3093, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:84 +[UP] flip: 19, stem: 6185, fault:37. flip_cnt: 2, stem_cnt: 94, fault_cnt:84 +[UP] flip: 29, stem: 3093, fault:37. flip_cnt: 2, stem_cnt: 94, fault_cnt:84 +[UP] flip: 34, stem: 3093, fault:37. flip_cnt: 2, stem_cnt: 94, fault_cnt:84 +[UP] flip: 17, stem: 3093, fault:37. flip_cnt: 2, stem_cnt: 94, fault_cnt:82 +[UP] flip: 31, stem: 3093, fault:37. flip_cnt: 2, stem_cnt: 94, fault_cnt:83 +[UP] flip: 37, stem: 3093, fault:37. flip_cnt: 2, stem_cnt: 94, fault_cnt:83 +[UP] flip: 5, stem: 3093, fault:37. flip_cnt: 2, stem_cnt: 94, fault_cnt:82 +[UP] flip: 37, stem: 3093, fault:37. flip_cnt: 2, stem_cnt: 94, fault_cnt:82 +[UP] flip: 123, stem: 6183, fault:37. flip_cnt: 9, stem_cnt: 93, fault_cnt:79 +[UP] flip: 21, stem: 12411, fault:37. flip_cnt: 1, stem_cnt: 86, fault_cnt:90 +[UP] flip: 22, stem: 37210, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:107 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 21834, fault:3. flip_cnt: 6, stem_cnt: 88, fault_cnt:62 +[UP] flip: 20, stem: 6241, fault:10. flip_cnt: 7, stem_cnt: 93, fault_cnt:47 +[UP] flip: 0, stem: 6248, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:44 +[UP] flip: 0, stem: 9367, fault:19. flip_cnt: 0, stem_cnt: 92, fault_cnt:48 +[UP] flip: 0, stem: 6245, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:53 +[UP] flip: 37, stem: 1, fault:19. flip_cnt: 7, stem_cnt: 95, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6253, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:44 +[UP] flip: 0, stem: 3128, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:45 +[UP] flip: 0, stem: 3129, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:44 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 12528, fault:3. flip_cnt: 3, stem_cnt: 84, fault_cnt:39 +[UP] flip: 28, stem: 9394, fault:9. flip_cnt: 11, stem_cnt: 92, fault_cnt:31 +[UP] flip: 0, stem: 6263, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:35 +[UP] flip: 0, stem: 6264, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:22 +[UP] flip: 0, stem: 9397, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:22 +[UP] flip: 0, stem: 12531, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:22 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 12549, fault:3. flip_cnt: 1, stem_cnt: 91, fault_cnt:37 +[UP] flip: 3, stem: 3, fault:9. flip_cnt: 1, stem_cnt: 93, fault_cnt:28 +[UP] flip: 0, stem: 3140, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:34 +[UP] flip: 0, stem: 3140, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:40 +[UP] flip: 23, stem: 1, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:43 +[UP] flip: 26, stem: 1, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:23 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 12577, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:52 +[UP] flip: 44, stem: 3, fault:10. flip_cnt: 19, stem_cnt: 93, fault_cnt:50 +[UP] flip: 44, stem: 2, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:55 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 12595, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:24 +[UP] flip: 3, stem: 9447, fault:10. flip_cnt: 1, stem_cnt: 93, fault_cnt:43 +[UP] flip: 0, stem: 3151, fault:21. flip_cnt: 0, stem_cnt: 94, fault_cnt:47 +[UP] flip: 9, stem: 3150, fault:21. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 36, stem: 6297, fault:21. flip_cnt: 7, stem_cnt: 94, fault_cnt:35 +[UP] flip: 55, stem: 3148, fault:21. flip_cnt: 10, stem_cnt: 95, fault_cnt:40 +[UP] flip: 42, stem: 3148, fault:21. flip_cnt: 7, stem_cnt: 95, fault_cnt:50 +[UP] flip: 88, stem: 2, fault:18. flip_cnt: 12, stem_cnt: 94, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 18944, fault:3. flip_cnt: 1, stem_cnt: 88, fault_cnt:29 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:52 +[UP] flip: 62, stem: 9474, fault:20. flip_cnt: 18, stem_cnt: 92, fault_cnt:38 +[UP] flip: 29, stem: 6320, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 12649, fault:3. flip_cnt: 3, stem_cnt: 91, fault_cnt:33 +[UP] flip: 19, stem: 3164, fault:10. flip_cnt: 7, stem_cnt: 94, fault_cnt:33 +[UP] flip: 38, stem: 3162, fault:19. flip_cnt: 11, stem_cnt: 95, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 18996, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:50 +[UP] flip: 44, stem: 3, fault:9. flip_cnt: 19, stem_cnt: 93, fault_cnt:76 +[UP] flip: 25, stem: 2, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:82 +[UP] flip: 57, stem: 3171, fault:20. flip_cnt: 15, stem_cnt: 93, fault_cnt:75 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 15864, fault:3. flip_cnt: 0, stem_cnt: 82, fault_cnt:36 +[UP] flip: 24, stem: 3173, fault:11. flip_cnt: 9, stem_cnt: 93, fault_cnt:44 +[UP] flip: 4, stem: 3174, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:46 +[UP] flip: 6, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:89 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 12705, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:37 +[UP] flip: 46, stem: 2, fault:10. flip_cnt: 19, stem_cnt: 94, fault_cnt:48 +[UP] flip: 25, stem: 2, fault:18. flip_cnt: 9, stem_cnt: 94, fault_cnt:52 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 12723, fault:3. flip_cnt: 8, stem_cnt: 89, fault_cnt:38 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:60 +[UP] flip: 15, stem: 3180, fault:23. flip_cnt: 5, stem_cnt: 95, fault_cnt:54 +[UP] flip: 14, stem: 1, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 41, stem: 3, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:46 +[UP] flip: 7, stem: 6365, fault:23. flip_cnt: 1, stem_cnt: 94, fault_cnt:63 +[UP] flip: 14, stem: 2, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:84 +[UP] flip: 70, stem: 3, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:79 +[UP] flip: 5, stem: 6370, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:85 +[UP] flip: 2, stem: 9558, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:84 +[UP] flip: 156, stem: 9560, fault:20. flip_cnt: 15, stem_cnt: 93, fault_cnt:98 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 15961, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:31 +[UP] flip: 2, stem: 3194, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:35 +[UP] flip: 8, stem: 9588, fault:20. flip_cnt: 3, stem_cnt: 85, fault_cnt:30 +[UP] flip: 8, stem: 6392, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:43 +[UP] flip: 31, stem: 2, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:36 +[UP] flip: 200, stem: 6390, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:34 +[UP] flip: 17, stem: 3197, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 19, stem: 3197, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 22, stem: 3197, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 16, stem: 3197, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 10, stem: 6396, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:64 +[UP] flip: 256, stem: 3197, fault:20. flip_cnt: 27, stem_cnt: 92, fault_cnt:68 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9616, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:23 +[UP] flip: 0, stem: 6415, fault:9. flip_cnt: 0, stem_cnt: 91, fault_cnt:25 +[UP] flip: 0, stem: 6413, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:24 +[UP] flip: 0, stem: 6417, fault:20. flip_cnt: 0, stem_cnt: 87, fault_cnt:24 +[UP] flip: 0, stem: 9628, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:24 +[UP] flip: 0, stem: 3209, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:24 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 34, stem: 12851, fault:3. flip_cnt: 19, stem_cnt: 89, fault_cnt:21 +[UP] flip: 7, stem: 6424, fault:10. flip_cnt: 4, stem_cnt: 94, fault_cnt:46 +[UP] flip: 33, stem: 3, fault:22. flip_cnt: 9, stem_cnt: 93, fault_cnt:60 +[UP] flip: 2, stem: 3213, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:110 +[UP] flip: 2, stem: 3213, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:110 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 9663, fault:3. flip_cnt: 3, stem_cnt: 84, fault_cnt:46 +[UP] flip: 0, stem: 6439, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:38 +[UP] flip: 8, stem: 3219, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 164, stem: 2, fault:23. flip_cnt: 37, stem_cnt: 94, fault_cnt:44 +[UP] flip: 9, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:56 +[UP] flip: 25, stem: 3219, fault:26. flip_cnt: 5, stem_cnt: 95, fault_cnt:57 +[UP] flip: 20, stem: 1, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 67, stem: 3, fault:26. flip_cnt: 9, stem_cnt: 93, fault_cnt:49 +[UP] flip: 8, stem: 1, fault:26. flip_cnt: 1, stem_cnt: 95, fault_cnt:92 +[UP] flip: 144, stem: 2, fault:20. flip_cnt: 15, stem_cnt: 94, fault_cnt:84 +[UP] flip: 0, stem: 3228, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:89 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9691, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:47 +[UP] flip: 0, stem: 3232, fault:10. flip_cnt: 0, stem_cnt: 94, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9700, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:57 +[UP] flip: 24, stem: 3235, fault:9. flip_cnt: 9, stem_cnt: 93, fault_cnt:81 +[UP] flip: 5, stem: 9707, fault:20. flip_cnt: 2, stem_cnt: 91, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6483, fault:3. flip_cnt: 0, stem_cnt: 85, fault_cnt:18 +[UP] flip: 21, stem: 6477, fault:12. flip_cnt: 7, stem_cnt: 93, fault_cnt:47 +[UP] flip: 112, stem: 2, fault:20. flip_cnt: 37, stem_cnt: 94, fault_cnt:46 +[UP] flip: 10, stem: 1, fault:22. flip_cnt: 2, stem_cnt: 95, fault_cnt:60 +[UP] flip: 94, stem: 2, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:48 +[UP] flip: 48, stem: 6486, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 1, stem: 16222, fault:3. flip_cnt: 1, stem_cnt: 89, fault_cnt:66 +[UP] flip: 6, stem: 12979, fault:10. flip_cnt: 2, stem_cnt: 92, fault_cnt:82 +[UP] flip: 13, stem: 12985, fault:19. flip_cnt: 4, stem_cnt: 91, fault_cnt:53 +[UP] flip: 0, stem: 12984, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:61 +[UP] flip: 13, stem: 19477, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:57 +[UP] flip: 20, stem: 9745, fault:19. flip_cnt: 4, stem_cnt: 93, fault_cnt:54 +[UP] flip: 98, stem: 2, fault:19. flip_cnt: 20, stem_cnt: 94, fault_cnt:49 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 13009, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:73 +[UP] flip: 6, stem: 3255, fault:9. flip_cnt: 2, stem_cnt: 93, fault_cnt:34 +[UP] flip: 10, stem: 13016, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:30 +[UP] flip: 28, stem: 6510, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:22 +[UP] flip: 0, stem: 9763, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:40 +[UP] flip: 0, stem: 16274, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 16296, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:32 +[UP] flip: 8, stem: 6521, fault:9. flip_cnt: 3, stem_cnt: 93, fault_cnt:47 +[UP] flip: 31, stem: 9784, fault:23. flip_cnt: 9, stem_cnt: 91, fault_cnt:43 +[UP] flip: 3, stem: 2, fault:23. flip_cnt: 1, stem_cnt: 94, fault_cnt:81 +[UP] flip: 100, stem: 3265, fault:20. flip_cnt: 19, stem_cnt: 93, fault_cnt:70 +[UP] flip: 51, stem: 6530, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:69 +[UP] flip: 6, stem: 3264, fault:19. flip_cnt: 1, stem_cnt: 95, fault_cnt:75 +[UP] flip: 59, stem: 3264, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:54 +[UP] flip: 0, stem: 3263, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 66, stem: 32691, fault:3. flip_cnt: 37, stem_cnt: 85, fault_cnt:20 +[UP] flip: 0, stem: 6539, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:50 +[UP] flip: 10, stem: 3271, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:61 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:61 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 13102, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:35 +[UP] flip: 2, stem: 9829, fault:10. flip_cnt: 1, stem_cnt: 91, fault_cnt:28 +[UP] flip: 10, stem: 6552, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:36 +[UP] flip: 14, stem: 6553, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:38 +[UP] flip: 171, stem: 2, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:29 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 13126, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:31 +[UP] flip: 0, stem: 16411, fault:9. flip_cnt: 0, stem_cnt: 90, fault_cnt:35 +[UP] flip: 5, stem: 9848, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:24 +[UP] flip: 145, stem: 3286, fault:24. flip_cnt: 37, stem_cnt: 93, fault_cnt:37 +[UP] flip: 12, stem: 3281, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 15, stem: 3281, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 18, stem: 3281, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 18, stem: 3281, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 18, stem: 3281, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 45, stem: 3281, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:56 +[UP] flip: 39, stem: 3281, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:55 +[UP] flip: 98, stem: 3284, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 12, stem: 6577, fault:24. flip_cnt: 1, stem_cnt: 93, fault_cnt:68 +[UP] flip: 22, stem: 3295, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:94 +[UP] flip: 24, stem: 3283, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:88 +[UP] flip: 96, stem: 6563, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:85 +[UP] flip: 26, stem: 3297, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:88 +[UP] flip: 10, stem: 3297, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:90 +[UP] flip: 36, stem: 6583, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:59 +[UP] flip: 132, stem: 6564, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:84 +[UP] flip: 277, stem: 3282, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:87 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 26433, fault:3. flip_cnt: 0, stem_cnt: 79, fault_cnt:18 +[UP] flip: 10, stem: 3303, fault:12. flip_cnt: 4, stem_cnt: 95, fault_cnt:50 +[UP] flip: 4, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:81 +[UP] flip: 52, stem: 2, fault:20. flip_cnt: 12, stem_cnt: 94, fault_cnt:72 +[UP] flip: 8, stem: 6614, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:71 +[UP] flip: 13, stem: 2, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:79 +[UP] flip: 58, stem: 3305, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:74 +[UP] flip: 8, stem: 13225, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:82 +[UP] flip: 4, stem: 6613, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:107 +[UP] flip: 5, stem: 6613, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:107 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 16571, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:34 +[UP] flip: 6, stem: 9947, fault:12. flip_cnt: 2, stem_cnt: 91, fault_cnt:59 +[UP] flip: 24, stem: 2, fault:18. flip_cnt: 7, stem_cnt: 94, fault_cnt:63 +[UP] flip: 8, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:64 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 6639, fault:3. flip_cnt: 4, stem_cnt: 93, fault_cnt:69 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 26568, fault:3. flip_cnt: 4, stem_cnt: 88, fault_cnt:50 +[UP] flip: 22, stem: 6645, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:38 +[UP] flip: 2, stem: 9968, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:98 +[UP] flip: 8, stem: 3325, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:41 +[UP] flip: 9, stem: 3324, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:76 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 13310, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:33 +[UP] flip: 28, stem: 3330, fault:10. flip_cnt: 11, stem_cnt: 93, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 6661, fault:3. flip_cnt: 4, stem_cnt: 93, fault_cnt:35 +[UP] flip: 3, stem: 3332, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:35 +[UP] flip: 0, stem: 5, fault:11. flip_cnt: 0, stem_cnt: 91, fault_cnt:28 +[UP] flip: 12, stem: 10001, fault:20. flip_cnt: 4, stem_cnt: 91, fault_cnt:17 +[UP] flip: 0, stem: 9999, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:39 +[UP] flip: 18, stem: 10000, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:31 +[UP] flip: 0, stem: 13336, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:22 +[UP] flip: 5, stem: 20010, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:17 +[UP] flip: 50, stem: 6676, fault:19. flip_cnt: 7, stem_cnt: 93, fault_cnt:27 +[UP] flip: 52, stem: 0, fault:19. flip_cnt: 7, stem_cnt: 96, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 20047, fault:3. flip_cnt: 3, stem_cnt: 89, fault_cnt:45 +[UP] flip: 0, stem: 10027, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:35 +[UP] flip: 0, stem: 6685, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:43 +[UP] flip: 14, stem: 10027, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:45 +[UP] flip: 184, stem: 10032, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:17 +[UP] flip: 5, stem: 6686, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:28 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 23437, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:30 +[UP] flip: 14, stem: 9, fault:9. flip_cnt: 7, stem_cnt: 87, fault_cnt:72 +[UP] flip: 8, stem: 10051, fault:20. flip_cnt: 2, stem_cnt: 92, fault_cnt:57 +[UP] flip: 18, stem: 3353, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:60 +[UP] flip: 125, stem: 3352, fault:20. flip_cnt: 27, stem_cnt: 93, fault_cnt:52 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 10063, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:40 +[UP] flip: 0, stem: 3357, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:21 +[UP] flip: 28, stem: 16781, fault:20. flip_cnt: 7, stem_cnt: 90, fault_cnt:28 +[UP] flip: 7, stem: 6713, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:22 +[UP] flip: 55, stem: 1, fault:19. flip_cnt: 13, stem_cnt: 95, fault_cnt:32 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 6722, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:42 +[UP] flip: 9, stem: 3370, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:38 +[UP] flip: 0, stem: 6725, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 10093, fault:3. flip_cnt: 4, stem_cnt: 92, fault_cnt:67 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 10100, fault:3. flip_cnt: 7, stem_cnt: 91, fault_cnt:18 +[UP] flip: 96, stem: 3369, fault:9. flip_cnt: 37, stem_cnt: 93, fault_cnt:49 +[UP] flip: 26, stem: 6736, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:64 +[UP] flip: 12, stem: 3374, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:61 +[UP] flip: 19, stem: 13481, fault:20. flip_cnt: 4, stem_cnt: 91, fault_cnt:62 +[UP] flip: 61, stem: 16851, fault:20. flip_cnt: 10, stem_cnt: 91, fault_cnt:41 +[UP] flip: 65, stem: 6739, fault:20. flip_cnt: 10, stem_cnt: 94, fault_cnt:51 +[UP] flip: 264, stem: 3369, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6751, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:33 +[UP] flip: 0, stem: 3377, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 16891, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:34 +[UP] flip: 3, stem: 6759, fault:9. flip_cnt: 1, stem_cnt: 93, fault_cnt:36 +[UP] flip: 15, stem: 3382, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:31 +[UP] flip: 10, stem: 10144, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:31 +[UP] flip: 40, stem: 13524, fault:20. flip_cnt: 8, stem_cnt: 93, fault_cnt:29 +[UP] flip: 38, stem: 6762, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:35 +[UP] flip: 17, stem: 6766, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:46 +[UP] flip: 17, stem: 10150, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:46 +[UP] flip: 6, stem: 3379, fault:19. flip_cnt: 1, stem_cnt: 95, fault_cnt:52 +[UP] flip: 31, stem: 3379, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:51 +[UP] flip: 39, stem: 6768, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:42 +[UP] flip: 20, stem: 6768, fault:19. flip_cnt: 2, stem_cnt: 93, fault_cnt:56 +[UP] flip: 135, stem: 3381, fault:19. flip_cnt: 11, stem_cnt: 94, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 13569, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:46 +[UP] flip: 14, stem: 3393, fault:9. flip_cnt: 9, stem_cnt: 94, fault_cnt:57 +[UP] flip: 15, stem: 10184, fault:20. flip_cnt: 4, stem_cnt: 91, fault_cnt:37 +[UP] flip: 0, stem: 13579, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:44 +[UP] flip: 33, stem: 6789, fault:20. flip_cnt: 7, stem_cnt: 95, fault_cnt:53 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 23787, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:43 +[UP] flip: 20, stem: 3400, fault:10. flip_cnt: 9, stem_cnt: 94, fault_cnt:48 +[UP] flip: 9, stem: 1, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:80 +[UP] flip: 56, stem: 1, fault:19. flip_cnt: 13, stem_cnt: 95, fault_cnt:59 +[UP] flip: 166, stem: 3399, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 13617, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:51 +[UP] flip: 94, stem: 3407, fault:9. flip_cnt: 37, stem_cnt: 93, fault_cnt:37 +[UP] flip: 8, stem: 10217, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 6817, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:22 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 23872, fault:3. flip_cnt: 1, stem_cnt: 87, fault_cnt:44 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:55 +[UP] flip: 13, stem: 3412, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:43 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:43 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 13665, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:34 +[UP] flip: 7, stem: 9, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:49 +[UP] flip: 14, stem: 20507, fault:20. flip_cnt: 4, stem_cnt: 89, fault_cnt:37 +[UP] flip: 12, stem: 23930, fault:20. flip_cnt: 3, stem_cnt: 86, fault_cnt:49 +[UP] flip: 0, stem: 3421, fault:24. flip_cnt: 0, stem_cnt: 94, fault_cnt:48 +[UP] flip: 51, stem: 3417, fault:19. flip_cnt: 8, stem_cnt: 94, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 20541, fault:3. flip_cnt: 1, stem_cnt: 87, fault_cnt:17 +[UP] flip: 22, stem: 1, fault:10. flip_cnt: 9, stem_cnt: 95, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 10279, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:32 +[UP] flip: 8, stem: 10280, fault:9. flip_cnt: 3, stem_cnt: 93, fault_cnt:32 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 20575, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:69 +[UP] flip: 85, stem: 6860, fault:9. flip_cnt: 37, stem_cnt: 93, fault_cnt:23 +[UP] flip: 23, stem: 6859, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:23 +[UP] flip: 0, stem: 13729, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:14 +[UP] flip: 0, stem: 3432, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:21 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 13749, fault:3. flip_cnt: 0, stem_cnt: 83, fault_cnt:53 +[UP] flip: 18, stem: 6873, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:54 +[UP] flip: 0, stem: 3438, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:53 +[UP] flip: 0, stem: 6874, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:50 +[UP] flip: 54, stem: 10314, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:52 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 20647, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:21 +[UP] flip: 3, stem: 3445, fault:9. flip_cnt: 1, stem_cnt: 92, fault_cnt:14 +[UP] flip: 26, stem: 3446, fault:20. flip_cnt: 7, stem_cnt: 92, fault_cnt:27 +[UP] flip: 37, stem: 1, fault:24. flip_cnt: 10, stem_cnt: 95, fault_cnt:49 +[UP] flip: 134, stem: 3442, fault:24. flip_cnt: 37, stem_cnt: 94, fault_cnt:52 +[UP] flip: 77, stem: 3444, fault:20. flip_cnt: 15, stem_cnt: 94, fault_cnt:68 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 13798, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:45 +[UP] flip: 27, stem: 3453, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:47 +[UP] flip: 4, stem: 13803, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:49 +[UP] flip: 0, stem: 10357, fault:24. flip_cnt: 0, stem_cnt: 92, fault_cnt:59 +[UP] flip: 6, stem: 6904, fault:24. flip_cnt: 1, stem_cnt: 94, fault_cnt:57 +[UP] flip: 19, stem: 1, fault:24. flip_cnt: 4, stem_cnt: 95, fault_cnt:73 +[UP] flip: 25, stem: 3452, fault:24. flip_cnt: 4, stem_cnt: 95, fault_cnt:65 +[UP] flip: 31, stem: 3452, fault:24. flip_cnt: 4, stem_cnt: 95, fault_cnt:62 +[UP] flip: 35, stem: 3452, fault:24. flip_cnt: 4, stem_cnt: 95, fault_cnt:59 +[UP] flip: 36, stem: 3452, fault:24. flip_cnt: 4, stem_cnt: 95, fault_cnt:55 +[UP] flip: 4, stem: 3452, fault:24. flip_cnt: 1, stem_cnt: 95, fault_cnt:97 +[UP] flip: 23, stem: 3450, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:95 +[UP] flip: 18, stem: 3450, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:95 +[UP] flip: 24, stem: 3450, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:95 +[UP] flip: 101, stem: 6888, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:90 +[UP] flip: 27, stem: 17266, fault:20. flip_cnt: 2, stem_cnt: 91, fault_cnt:99 +[UP] flip: 12, stem: 17296, fault:20. flip_cnt: 1, stem_cnt: 86, fault_cnt:93 +[UP] flip: 17, stem: 3452, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:74 +[UP] flip: 634, stem: 3460, fault:20. flip_cnt: 37, stem_cnt: 94, fault_cnt:73 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 11, stem: 17347, fault:3. flip_cnt: 7, stem_cnt: 89, fault_cnt:16 +[UP] flip: 7, stem: 9, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:47 +[UP] flip: 0, stem: 6943, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:43 +[UP] flip: 162, stem: 10418, fault:24. flip_cnt: 37, stem_cnt: 91, fault_cnt:31 +[UP] flip: 0, stem: 3473, fault:24. flip_cnt: 0, stem_cnt: 95, fault_cnt:50 +[UP] flip: 17, stem: 3473, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 19, stem: 3473, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 20, stem: 3473, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 20, stem: 3473, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 21, stem: 3473, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 31, stem: 3473, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 9, stem: 6952, fault:24. flip_cnt: 1, stem_cnt: 94, fault_cnt:45 +[UP] flip: 32, stem: 3472, fault:33. flip_cnt: 4, stem_cnt: 95, fault_cnt:52 +[UP] flip: 3, stem: 1, fault:33. flip_cnt: 1, stem_cnt: 95, fault_cnt:87 +[UP] flip: 108, stem: 6943, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:82 +[UP] flip: 210, stem: 3473, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:85 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 20, stem: 10460, fault:3. flip_cnt: 11, stem_cnt: 91, fault_cnt:26 +[UP] flip: 6, stem: 6976, fault:10. flip_cnt: 2, stem_cnt: 92, fault_cnt:35 +[UP] flip: 11, stem: 10463, fault:22. flip_cnt: 3, stem_cnt: 93, fault_cnt:43 +[UP] flip: 12, stem: 3487, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 14, stem: 3487, fault:22. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 12, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:77 +[UP] flip: 9, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:77 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 10483, fault:3. flip_cnt: 7, stem_cnt: 92, fault_cnt:33 +[UP] flip: 3, stem: 3496, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:37 +[UP] flip: 73, stem: 6991, fault:24. flip_cnt: 24, stem_cnt: 94, fault_cnt:44 +[UP] flip: 19, stem: 6995, fault:24. flip_cnt: 4, stem_cnt: 93, fault_cnt:29 +[UP] flip: 33, stem: 3495, fault:24. flip_cnt: 7, stem_cnt: 94, fault_cnt:35 +[UP] flip: 20, stem: 6993, fault:24. flip_cnt: 3, stem_cnt: 94, fault_cnt:30 +[UP] flip: 34, stem: 6993, fault:24. flip_cnt: 7, stem_cnt: 94, fault_cnt:35 +[UP] flip: 19, stem: 3501, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 22, stem: 3494, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 24, stem: 3494, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 27, stem: 3494, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 27, stem: 3494, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 22, stem: 3508, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:67 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 28065, fault:3. flip_cnt: 0, stem_cnt: 87, fault_cnt:14 +[UP] flip: 0, stem: 7019, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:26 +[UP] flip: 0, stem: 7026, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:23 +[UP] flip: 0, stem: 10534, fault:24. flip_cnt: 0, stem_cnt: 92, fault_cnt:39 +[UP] flip: 0, stem: 7023, fault:24. flip_cnt: 0, stem_cnt: 94, fault_cnt:39 +[UP] flip: 64, stem: 3511, fault:20. flip_cnt: 12, stem_cnt: 94, fault_cnt:44 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 14061, fault:3. flip_cnt: 4, stem_cnt: 91, fault_cnt:35 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:38 +[UP] flip: 0, stem: 3517, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 10560, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:69 +[UP] flip: 3, stem: 7043, fault:9. flip_cnt: 1, stem_cnt: 91, fault_cnt:20 +[UP] flip: 0, stem: 7048, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:17 +[UP] flip: 29, stem: 17611, fault:20. flip_cnt: 7, stem_cnt: 90, fault_cnt:41 +[UP] flip: 61, stem: 3523, fault:19. flip_cnt: 16, stem_cnt: 94, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 24676, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:69 +[UP] flip: 9, stem: 3527, fault:9. flip_cnt: 3, stem_cnt: 94, fault_cnt:43 +[UP] flip: 0, stem: 3528, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:51 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 7059, fault:3. flip_cnt: 3, stem_cnt: 93, fault_cnt:31 +[UP] flip: 20, stem: 2, fault:10. flip_cnt: 7, stem_cnt: 94, fault_cnt:32 +[UP] flip: 113, stem: 2, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:40 +[UP] flip: 13, stem: 1, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:57 +[UP] flip: 37, stem: 2, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:52 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 24746, fault:3. flip_cnt: 7, stem_cnt: 88, fault_cnt:29 +[UP] flip: 17, stem: 14145, fault:12. flip_cnt: 9, stem_cnt: 90, fault_cnt:36 +[UP] flip: 3, stem: 10611, fault:18. flip_cnt: 1, stem_cnt: 91, fault_cnt:39 +[UP] flip: 34, stem: 17683, fault:24. flip_cnt: 9, stem_cnt: 91, fault_cnt:45 +[UP] flip: 5, stem: 17690, fault:20. flip_cnt: 1, stem_cnt: 90, fault_cnt:88 +[UP] flip: 0, stem: 24770, fault:20. flip_cnt: 0, stem_cnt: 90, fault_cnt:92 +[UP] flip: 40, stem: 7071, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:99 +[UP] flip: 16, stem: 14154, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:99 +[UP] flip: 16, stem: 3536, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 7093, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:37 +[UP] flip: 11, stem: 7095, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:42 +[UP] flip: 9, stem: 14189, fault:20. flip_cnt: 3, stem_cnt: 91, fault_cnt:35 +[UP] flip: 14, stem: 10645, fault:19. flip_cnt: 3, stem_cnt: 92, fault_cnt:29 +[UP] flip: 37, stem: 7098, fault:19. flip_cnt: 9, stem_cnt: 92, fault_cnt:28 +[UP] flip: 30, stem: 14200, fault:19. flip_cnt: 7, stem_cnt: 86, fault_cnt:82 +[UP] flip: 13, stem: 7099, fault:19. flip_cnt: 2, stem_cnt: 93, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 17766, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:39 +[UP] flip: 0, stem: 3555, fault:10. flip_cnt: 0, stem_cnt: 94, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 14225, fault:3. flip_cnt: 4, stem_cnt: 91, fault_cnt:40 +[UP] flip: 11, stem: 3558, fault:9. flip_cnt: 4, stem_cnt: 94, fault_cnt:21 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 7121, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:41 +[UP] flip: 23, stem: 3564, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:33 +[UP] flip: 3, stem: 10687, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:35 +[UP] flip: 0, stem: 7127, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:34 +[UP] flip: 3, stem: 3565, fault:19. flip_cnt: 1, stem_cnt: 93, fault_cnt:67 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 14265, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:41 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 10710, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:49 +[UP] flip: 0, stem: 7147, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:45 +[UP] flip: 0, stem: 7143, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:62 +[UP] flip: 0, stem: 3572, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:56 +[UP] flip: 0, stem: 10714, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:56 +[UP] flip: 176, stem: 3570, fault:20. flip_cnt: 37, stem_cnt: 94, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 10737, fault:3. flip_cnt: 3, stem_cnt: 84, fault_cnt:44 +[UP] flip: 9, stem: 7153, fault:10. flip_cnt: 3, stem_cnt: 94, fault_cnt:38 +[UP] flip: 8, stem: 0, fault:19. flip_cnt: 2, stem_cnt: 96, fault_cnt:79 +[UP] flip: 5, stem: 0, fault:19. flip_cnt: 2, stem_cnt: 96, fault_cnt:80 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 7163, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:20 +[UP] flip: 5, stem: 2, fault:9. flip_cnt: 2, stem_cnt: 94, fault_cnt:25 +[UP] flip: 0, stem: 3584, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:30 +[UP] flip: 0, stem: 7166, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:30 +[UP] flip: 0, stem: 10751, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:30 +[UP] flip: 0, stem: 14335, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:30 +[UP] flip: 0, stem: 17921, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 10768, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 10774, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:64 +[UP] flip: 20, stem: 7184, fault:9. flip_cnt: 9, stem_cnt: 93, fault_cnt:47 +[UP] flip: 8, stem: 14373, fault:20. flip_cnt: 3, stem_cnt: 91, fault_cnt:35 +[UP] flip: 4, stem: 21561, fault:20. flip_cnt: 2, stem_cnt: 91, fault_cnt:37 +[UP] flip: 24, stem: 10781, fault:19. flip_cnt: 5, stem_cnt: 93, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 17987, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:26 +[UP] flip: 8, stem: 7201, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:36 +[UP] flip: 104, stem: 10799, fault:20. flip_cnt: 37, stem_cnt: 91, fault_cnt:18 +[UP] flip: 27, stem: 3599, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:53 +[UP] flip: 55, stem: 32403, fault:20. flip_cnt: 19, stem_cnt: 87, fault_cnt:37 +[UP] flip: 11, stem: 3601, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 14, stem: 3601, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 11, stem: 3601, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 19, stem: 3601, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 20, stem: 3601, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 18, stem: 3601, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 24, stem: 3601, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 86, stem: 7199, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:53 +[UP] flip: 9, stem: 10805, fault:24. flip_cnt: 1, stem_cnt: 94, fault_cnt:59 +[UP] flip: 12, stem: 18005, fault:24. flip_cnt: 1, stem_cnt: 91, fault_cnt:93 +[UP] flip: 1, stem: 18005, fault:24. flip_cnt: 1, stem_cnt: 91, fault_cnt:93 +[UP] flip: 0, stem: 18049, fault:24. flip_cnt: 0, stem_cnt: 91, fault_cnt:97 +[UP] flip: 109, stem: 3600, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:80 +[UP] flip: 17, stem: 21615, fault:20. flip_cnt: 1, stem_cnt: 90, fault_cnt:86 +[UP] flip: 17, stem: 10799, fault:19. flip_cnt: 1, stem_cnt: 87, fault_cnt:77 +[UP] flip: 55, stem: 7198, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:59 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 14477, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:46 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:30 +[UP] flip: 0, stem: 3621, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:27 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 21747, fault:3. flip_cnt: 3, stem_cnt: 81, fault_cnt:52 +[UP] flip: 19, stem: 10872, fault:9. flip_cnt: 7, stem_cnt: 93, fault_cnt:58 +[UP] flip: 0, stem: 7249, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:38 +[UP] flip: 0, stem: 7252, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:35 +[UP] flip: 0, stem: 10877, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:35 +[UP] flip: 58, stem: 14505, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:35 +[UP] flip: 81, stem: 1, fault:19. flip_cnt: 15, stem_cnt: 95, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 10895, fault:3. flip_cnt: 2, stem_cnt: 91, fault_cnt:29 +[UP] flip: 76, stem: 10898, fault:9. flip_cnt: 37, stem_cnt: 91, fault_cnt:14 +[UP] flip: 28, stem: 18163, fault:20. flip_cnt: 9, stem_cnt: 90, fault_cnt:32 +[UP] flip: 7, stem: 14535, fault:20. flip_cnt: 2, stem_cnt: 90, fault_cnt:38 +[UP] flip: 10, stem: 3636, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:80 +[UP] flip: 12, stem: 7267, fault:19. flip_cnt: 2, stem_cnt: 93, fault_cnt:83 +[UP] flip: 65, stem: 7271, fault:19. flip_cnt: 11, stem_cnt: 93, fault_cnt:78 +[UP] flip: 6, stem: 3639, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:88 +[UP] flip: 17, stem: 3640, fault:29. flip_cnt: 4, stem_cnt: 94, fault_cnt:87 +[UP] flip: 8, stem: 10911, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:84 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 21853, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:56 +[UP] flip: 11, stem: 2, fault:9. flip_cnt: 4, stem_cnt: 94, fault_cnt:44 +[UP] flip: 6, stem: 3644, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:72 +[UP] flip: 10, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:75 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 7296, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:80 +[UP] flip: 3, stem: 10945, fault:9. flip_cnt: 1, stem_cnt: 92, fault_cnt:77 +[UP] flip: 0, stem: 14597, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:15 +[UP] flip: 21, stem: 3647, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:55 +[UP] flip: 13, stem: 3647, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 16, stem: 3647, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 17, stem: 3647, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 14, stem: 3647, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 24, stem: 3647, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 21, stem: 3647, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 91, stem: 7296, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 81, stem: 14613, fault:20. flip_cnt: 7, stem_cnt: 92, fault_cnt:60 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 10981, fault:3. flip_cnt: 3, stem_cnt: 92, fault_cnt:24 +[UP] flip: 24, stem: 3664, fault:12. flip_cnt: 9, stem_cnt: 92, fault_cnt:40 +[UP] flip: 5, stem: 1, fault:18. flip_cnt: 2, stem_cnt: 95, fault_cnt:80 +[UP] flip: 2, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:80 +[UP] flip: 11, stem: 3666, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:79 +[UP] flip: 11, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:92 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 14670, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:18 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 22017, fault:3. flip_cnt: 9, stem_cnt: 87, fault_cnt:50 +[UP] flip: 4, stem: 11009, fault:9. flip_cnt: 2, stem_cnt: 93, fault_cnt:52 +[UP] flip: 8, stem: 7346, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:51 +[UP] flip: 10, stem: 7342, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:52 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 18371, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:18 +[UP] flip: 7, stem: 9, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:52 +[UP] flip: 16, stem: 18379, fault:20. flip_cnt: 4, stem_cnt: 90, fault_cnt:34 +[UP] flip: 11, stem: 7354, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:61 +[UP] flip: 6, stem: 11033, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:52 +[UP] flip: 40, stem: 14711, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:51 +[UP] flip: 63, stem: 11035, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:50 +[UP] flip: 23, stem: 3683, fault:19. flip_cnt: 4, stem_cnt: 93, fault_cnt:44 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11050, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:70 +[UP] flip: 24, stem: 7369, fault:9. flip_cnt: 11, stem_cnt: 93, fault_cnt:60 +[UP] flip: 11, stem: 7371, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:59 +[UP] flip: 11, stem: 7373, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:61 +[UP] flip: 23, stem: 7375, fault:20. flip_cnt: 5, stem_cnt: 93, fault_cnt:61 +[UP] flip: 44, stem: 3685, fault:26. flip_cnt: 9, stem_cnt: 93, fault_cnt:52 +[UP] flip: 11, stem: 14750, fault:26. flip_cnt: 2, stem_cnt: 92, fault_cnt:74 +[UP] flip: 26, stem: 14756, fault:26. flip_cnt: 4, stem_cnt: 93, fault_cnt:53 +[UP] flip: 22, stem: 3688, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 30, stem: 3688, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 24, stem: 3688, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 39, stem: 3688, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 28, stem: 3688, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 65, stem: 3688, fault:26. flip_cnt: 5, stem_cnt: 95, fault_cnt:52 +[UP] flip: 31, stem: 3688, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 59, stem: 3688, fault:26. flip_cnt: 5, stem_cnt: 95, fault_cnt:53 +[UP] flip: 129, stem: 7363, fault:26. flip_cnt: 9, stem_cnt: 93, fault_cnt:48 +[UP] flip: 15, stem: 3685, fault:26. flip_cnt: 1, stem_cnt: 94, fault_cnt:95 +[UP] flip: 27, stem: 11102, fault:26. flip_cnt: 2, stem_cnt: 94, fault_cnt:98 +[UP] flip: 29, stem: 2, fault:26. flip_cnt: 2, stem_cnt: 94, fault_cnt:95 +[UP] flip: 125, stem: 3, fault:26. flip_cnt: 9, stem_cnt: 93, fault_cnt:90 +[UP] flip: 15, stem: 33244, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:97 +[UP] flip: 16, stem: 18454, fault:20. flip_cnt: 1, stem_cnt: 86, fault_cnt:106 +[UP] flip: 3, stem: 22132, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:97 +[UP] flip: 17, stem: 14749, fault:20. flip_cnt: 1, stem_cnt: 87, fault_cnt:90 +[UP] flip: 57, stem: 140614, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:72 +[UP] flip: 149, stem: 11111, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:104 +[UP] flip: 150, stem: 7402, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:104 +[UP] flip: 21, stem: 22157, fault:20. flip_cnt: 1, stem_cnt: 86, fault_cnt:104 +[UP] flip: 48, stem: 51763, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:69 +[UP] flip: 37, stem: 218609, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:51 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 18576, fault:3. flip_cnt: 4, stem_cnt: 90, fault_cnt:60 +[UP] flip: 0, stem: 14865, fault:9. flip_cnt: 0, stem_cnt: 91, fault_cnt:71 +[UP] flip: 23, stem: 11149, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:60 +[UP] flip: 16, stem: 7436, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:59 +[UP] flip: 12, stem: 7437, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:56 +[UP] flip: 16, stem: 0, fault:19. flip_cnt: 3, stem_cnt: 96, fault_cnt:58 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 14891, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:74 +[UP] flip: 26, stem: 11171, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:56 +[UP] flip: 17, stem: 11173, fault:20. flip_cnt: 7, stem_cnt: 92, fault_cnt:43 +[UP] flip: 0, stem: 7449, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 14910, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:36 +[UP] flip: 0, stem: 3729, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:44 +[UP] flip: 0, stem: 14917, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 19, stem: 11194, fault:3. flip_cnt: 11, stem_cnt: 92, fault_cnt:69 +[UP] flip: 27, stem: 3733, fault:9. flip_cnt: 10, stem_cnt: 94, fault_cnt:42 +[UP] flip: 105, stem: 3735, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:20 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 18676, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:35 +[UP] flip: 24, stem: 1, fault:9. flip_cnt: 9, stem_cnt: 95, fault_cnt:44 +[UP] flip: 12, stem: 7473, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:56 +[UP] flip: 16, stem: 0, fault:19. flip_cnt: 4, stem_cnt: 96, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 24, stem: 22441, fault:3. flip_cnt: 15, stem_cnt: 89, fault_cnt:32 +[UP] flip: 9, stem: 7487, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:54 +[UP] flip: 12, stem: 11224, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:46 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:55 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:55 +[UP] flip: 22, stem: 0, fault:20. flip_cnt: 4, stem_cnt: 96, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 14989, fault:3. flip_cnt: 4, stem_cnt: 91, fault_cnt:40 +[UP] flip: 8, stem: 7505, fault:9. flip_cnt: 3, stem_cnt: 85, fault_cnt:43 +[UP] flip: 13, stem: 7500, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:25 +[UP] flip: 40, stem: 3750, fault:19. flip_cnt: 10, stem_cnt: 95, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 46, stem: 18761, fault:3. flip_cnt: 32, stem_cnt: 90, fault_cnt:38 +[UP] flip: 12, stem: 11266, fault:10. flip_cnt: 5, stem_cnt: 85, fault_cnt:94 +[UP] flip: 36, stem: 7509, fault:19. flip_cnt: 11, stem_cnt: 93, fault_cnt:60 +[UP] flip: 149, stem: 2, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 7517, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:42 +[UP] flip: 8, stem: 8, fault:9. flip_cnt: 3, stem_cnt: 88, fault_cnt:50 +[UP] flip: 0, stem: 7519, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:49 +[UP] flip: 0, stem: 3759, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:52 +[UP] flip: 41, stem: 1, fault:19. flip_cnt: 7, stem_cnt: 95, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 54, stem: 26343, fault:3. flip_cnt: 37, stem_cnt: 87, fault_cnt:13 +[UP] flip: 15, stem: 18821, fault:9. flip_cnt: 7, stem_cnt: 90, fault_cnt:24 +[UP] flip: 3, stem: 26353, fault:20. flip_cnt: 1, stem_cnt: 89, fault_cnt:26 +[UP] flip: 40, stem: 7527, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:20 +[UP] flip: 0, stem: 22584, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:21 +[UP] flip: 0, stem: 22584, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:21 +[UP] flip: 22, stem: 0, fault:19. flip_cnt: 4, stem_cnt: 96, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 3774, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 15094, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:48 +[UP] flip: 20, stem: 2, fault:10. flip_cnt: 7, stem_cnt: 94, fault_cnt:53 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 7553, fault:3. flip_cnt: 2, stem_cnt: 93, fault_cnt:25 +[UP] flip: 14, stem: 3778, fault:9. flip_cnt: 6, stem_cnt: 94, fault_cnt:64 +[UP] flip: 27, stem: 11335, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:62 +[UP] flip: 9, stem: 7560, fault:24. flip_cnt: 2, stem_cnt: 92, fault_cnt:55 +[UP] flip: 18, stem: 7561, fault:24. flip_cnt: 4, stem_cnt: 93, fault_cnt:61 +[UP] flip: 8, stem: 11343, fault:24. flip_cnt: 2, stem_cnt: 92, fault_cnt:59 +[UP] flip: 24, stem: 7560, fault:24. flip_cnt: 3, stem_cnt: 94, fault_cnt:46 +[UP] flip: 21, stem: 7561, fault:24. flip_cnt: 3, stem_cnt: 94, fault_cnt:47 +[UP] flip: 8, stem: 7567, fault:24. flip_cnt: 2, stem_cnt: 93, fault_cnt:53 +[UP] flip: 46, stem: 11348, fault:24. flip_cnt: 5, stem_cnt: 93, fault_cnt:50 +[UP] flip: 24, stem: 3778, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 24, stem: 3778, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 28, stem: 3778, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 32, stem: 3778, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 31, stem: 3778, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 118, stem: 7557, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:50 +[UP] flip: 163, stem: 3779, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:82 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11383, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:60 +[UP] flip: 9, stem: 3795, fault:9. flip_cnt: 3, stem_cnt: 95, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 10, stem: 34175, fault:3. flip_cnt: 9, stem_cnt: 85, fault_cnt:31 +[UP] flip: 8, stem: 18997, fault:9. flip_cnt: 3, stem_cnt: 83, fault_cnt:33 +[UP] flip: 31, stem: 18994, fault:20. flip_cnt: 9, stem_cnt: 90, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 15205, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:20 +[UP] flip: 5, stem: 1, fault:9. flip_cnt: 2, stem_cnt: 95, fault_cnt:35 +[UP] flip: 89, stem: 7604, fault:20. flip_cnt: 27, stem_cnt: 94, fault_cnt:23 +[UP] flip: 5, stem: 11410, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:31 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 15231, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:45 +[UP] flip: 0, stem: 3809, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:68 +[UP] flip: 16, stem: 7619, fault:20. flip_cnt: 5, stem_cnt: 93, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 11435, fault:3. flip_cnt: 2, stem_cnt: 91, fault_cnt:18 +[UP] flip: 3, stem: 7627, fault:9. flip_cnt: 1, stem_cnt: 91, fault_cnt:36 +[UP] flip: 10, stem: 3819, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:39 +[UP] flip: 124, stem: 19068, fault:20. flip_cnt: 37, stem_cnt: 90, fault_cnt:24 +[UP] flip: 0, stem: 15259, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:48 +[UP] flip: 28, stem: 11443, fault:20. flip_cnt: 5, stem_cnt: 93, fault_cnt:46 +[UP] flip: 0, stem: 11448, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:41 +[UP] flip: 14, stem: 7629, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:54 +[UP] flip: 19, stem: 3811, fault:28. flip_cnt: 3, stem_cnt: 95, fault_cnt:58 +[UP] flip: 39, stem: 3811, fault:28. flip_cnt: 5, stem_cnt: 95, fault_cnt:62 +[UP] flip: 72, stem: 3814, fault:28. flip_cnt: 9, stem_cnt: 93, fault_cnt:57 +[UP] flip: 13, stem: 11458, fault:19. flip_cnt: 1, stem_cnt: 93, fault_cnt:62 +[UP] flip: 369, stem: 7635, fault:19. flip_cnt: 37, stem_cnt: 93, fault_cnt:66 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 7652, fault:3. flip_cnt: 7, stem_cnt: 92, fault_cnt:24 +[UP] flip: 9, stem: 3825, fault:10. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 0, stem: 7655, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:51 +[UP] flip: 22, stem: 7656, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 14, stem: 11485, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:49 +[UP] flip: 200, stem: 3832, fault:19. flip_cnt: 37, stem_cnt: 93, fault_cnt:30 +[UP] flip: 55, stem: 3, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:45 +[UP] flip: 8, stem: 3834, fault:19. flip_cnt: 1, stem_cnt: 93, fault_cnt:63 +[UP] flip: 57, stem: 3835, fault:19. flip_cnt: 7, stem_cnt: 93, fault_cnt:91 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 11507, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:23 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 19186, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:30 +[UP] flip: 17, stem: 3839, fault:9. flip_cnt: 7, stem_cnt: 94, fault_cnt:54 +[UP] flip: 112, stem: 7680, fault:20. flip_cnt: 37, stem_cnt: 92, fault_cnt:62 +[UP] flip: 2, stem: 11517, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:89 +[UP] flip: 59, stem: 7683, fault:20. flip_cnt: 12, stem_cnt: 93, fault_cnt:77 +[UP] flip: 19, stem: 3837, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:76 +[UP] flip: 19, stem: 3837, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:76 +[UP] flip: 20, stem: 3837, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:76 +[UP] flip: 19, stem: 3837, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:76 +[UP] flip: 38, stem: 3837, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:76 +[UP] flip: 45, stem: 3837, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:76 +[UP] flip: 86, stem: 3840, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:75 +[UP] flip: 13, stem: 11529, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:86 +[UP] flip: 408, stem: 7691, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:78 +[UP] flip: 8, stem: 3842, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:76 +[UP] flip: 256, stem: 1, fault:20. flip_cnt: 17, stem_cnt: 95, fault_cnt:82 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 15417, fault:3. flip_cnt: 2, stem_cnt: 91, fault_cnt:31 +[UP] flip: 8, stem: 7709, fault:12. flip_cnt: 5, stem_cnt: 94, fault_cnt:50 +[UP] flip: 11, stem: 1, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 32, stem: 3, fault:22. flip_cnt: 9, stem_cnt: 93, fault_cnt:47 +[UP] flip: 6, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:78 +[UP] flip: 9, stem: 2, fault:26. flip_cnt: 2, stem_cnt: 94, fault_cnt:78 +[UP] flip: 59, stem: 3, fault:26. flip_cnt: 9, stem_cnt: 93, fault_cnt:73 +[UP] flip: 5, stem: 3864, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:84 +[UP] flip: 1, stem: 7725, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:84 +[UP] flip: 18, stem: 50210, fault:20. flip_cnt: 2, stem_cnt: 92, fault_cnt:110 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 19326, fault:3. flip_cnt: 4, stem_cnt: 90, fault_cnt:49 +[UP] flip: 87, stem: 7734, fault:10. flip_cnt: 35, stem_cnt: 92, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 11613, fault:3. flip_cnt: 3, stem_cnt: 84, fault_cnt:41 +[UP] flip: 20, stem: 15478, fault:9. flip_cnt: 7, stem_cnt: 90, fault_cnt:28 +[UP] flip: 15, stem: 7740, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:32 +[UP] flip: 10, stem: 19349, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:39 +[UP] flip: 0, stem: 7742, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:40 +[UP] flip: 33, stem: 7740, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:39 +[UP] flip: 17, stem: 19349, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:39 +[UP] flip: 0, stem: 7744, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:24 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 11634, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:84 +[UP] flip: 21, stem: 11633, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:83 +[UP] flip: 0, stem: 27154, fault:20. flip_cnt: 0, stem_cnt: 88, fault_cnt:17 +[UP] flip: 0, stem: 31035, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:23 +[UP] flip: 0, stem: 11641, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:44 +[UP] flip: 39, stem: 7759, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:32 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 1, stem: 7772, fault:3. flip_cnt: 1, stem_cnt: 90, fault_cnt:18 +[UP] flip: 0, stem: 11656, fault:10. flip_cnt: 0, stem_cnt: 92, fault_cnt:24 +[UP] flip: 0, stem: 11661, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:24 +[UP] flip: 0, stem: 7772, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:24 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 32, stem: 23336, fault:3. flip_cnt: 16, stem_cnt: 88, fault_cnt:26 +[UP] flip: 14, stem: 7782, fault:9. flip_cnt: 7, stem_cnt: 92, fault_cnt:24 +[UP] flip: 66, stem: 7780, fault:20. flip_cnt: 23, stem_cnt: 94, fault_cnt:34 +[UP] flip: 38, stem: 3891, fault:20. flip_cnt: 10, stem_cnt: 95, fault_cnt:42 +[UP] flip: 5, stem: 3889, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:62 +[UP] flip: 28, stem: 3895, fault:26. flip_cnt: 5, stem_cnt: 94, fault_cnt:63 +[UP] flip: 17, stem: 1, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:56 +[UP] flip: 25, stem: 1, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 63, stem: 3891, fault:26. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 10, stem: 7789, fault:26. flip_cnt: 1, stem_cnt: 94, fault_cnt:64 +[UP] flip: 10, stem: 3892, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:91 +[UP] flip: 181, stem: 1, fault:19. flip_cnt: 17, stem_cnt: 95, fault_cnt:90 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 11715, fault:3. flip_cnt: 3, stem_cnt: 84, fault_cnt:51 +[UP] flip: 22, stem: 15611, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:42 +[UP] flip: 8, stem: 27324, fault:20. flip_cnt: 3, stem_cnt: 89, fault_cnt:30 +[UP] flip: 158, stem: 3907, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:43 +[UP] flip: 71, stem: 3908, fault:20. flip_cnt: 15, stem_cnt: 93, fault_cnt:49 +[UP] flip: 46, stem: 3907, fault:20. flip_cnt: 7, stem_cnt: 95, fault_cnt:51 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 27364, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:43 +[UP] flip: 7, stem: 3911, fault:9. flip_cnt: 3, stem_cnt: 94, fault_cnt:68 +[UP] flip: 33, stem: 7823, fault:20. flip_cnt: 10, stem_cnt: 93, fault_cnt:44 +[UP] flip: 133, stem: 2, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11743, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:43 +[UP] flip: 18, stem: 3, fault:9. flip_cnt: 8, stem_cnt: 93, fault_cnt:46 +[UP] flip: 12, stem: 1, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 43, stem: 3, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:46 +[UP] flip: 6, stem: 3919, fault:23. flip_cnt: 1, stem_cnt: 94, fault_cnt:45 +[UP] flip: 7, stem: 3916, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:72 +[UP] flip: 1, stem: 3916, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:72 +[UP] flip: 14, stem: 3922, fault:28. flip_cnt: 2, stem_cnt: 94, fault_cnt:80 +[UP] flip: 60, stem: 3, fault:28. flip_cnt: 9, stem_cnt: 93, fault_cnt:70 +[UP] flip: 6, stem: 7839, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:81 +[UP] flip: 0, stem: 3924, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:105 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1, fault:3. flip_cnt: 0, stem_cnt: 95, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 11787, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:67 +[UP] flip: 6, stem: 7859, fault:9. flip_cnt: 2, stem_cnt: 93, fault_cnt:74 +[UP] flip: 10, stem: 3931, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:54 +[UP] flip: 29, stem: 7861, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:37 +[UP] flip: 131, stem: 11794, fault:20. flip_cnt: 27, stem_cnt: 92, fault_cnt:38 +[UP] flip: 20, stem: 3934, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:31 +[UP] flip: 117, stem: 3936, fault:19. flip_cnt: 19, stem_cnt: 92, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 3945, fault:3. flip_cnt: 3, stem_cnt: 86, fault_cnt:48 +[UP] flip: 0, stem: 3938, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:67 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 27574, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:34 +[UP] flip: 32, stem: 7880, fault:9. flip_cnt: 15, stem_cnt: 93, fault_cnt:22 +[UP] flip: 22, stem: 2, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:42 +[UP] flip: 0, stem: 3942, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 23667, fault:3. flip_cnt: 9, stem_cnt: 87, fault_cnt:77 +[UP] flip: 9, stem: 7889, fault:10. flip_cnt: 3, stem_cnt: 94, fault_cnt:50 +[UP] flip: 7, stem: 7890, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:50 +[UP] flip: 20, stem: 7891, fault:19. flip_cnt: 5, stem_cnt: 94, fault_cnt:52 +[UP] flip: 41, stem: 3950, fault:19. flip_cnt: 7, stem_cnt: 93, fault_cnt:41 +[UP] flip: 15, stem: 3944, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 16, stem: 3944, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 17, stem: 3944, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 29, stem: 3944, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 25, stem: 3944, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 29, stem: 3944, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 13, stem: 2, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:80 +[UP] flip: 340, stem: 3959, fault:19. flip_cnt: 27, stem_cnt: 92, fault_cnt:71 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 15833, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:41 +[UP] flip: 0, stem: 15837, fault:9. flip_cnt: 0, stem_cnt: 91, fault_cnt:34 +[UP] flip: 7, stem: 11882, fault:20. flip_cnt: 2, stem_cnt: 91, fault_cnt:35 +[UP] flip: 54, stem: 15842, fault:20. flip_cnt: 12, stem_cnt: 92, fault_cnt:24 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 19817, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:32 +[UP] flip: 0, stem: 3965, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:25 +[UP] flip: 0, stem: 1, fault:11. flip_cnt: 0, stem_cnt: 95, fault_cnt:18 +[UP] flip: 0, stem: 3976, fault:20. flip_cnt: 0, stem_cnt: 85, fault_cnt:18 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 23809, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:32 +[UP] flip: 3, stem: 2, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:31 +[UP] flip: 36, stem: 3971, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:28 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 44, stem: 23833, fault:3. flip_cnt: 37, stem_cnt: 89, fault_cnt:12 +[UP] flip: 5, stem: 2, fault:9. flip_cnt: 2, stem_cnt: 94, fault_cnt:45 +[UP] flip: 10, stem: 3975, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:55 +[UP] flip: 12, stem: 3975, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 17, stem: 2, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:53 +[UP] flip: 37, stem: 7951, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:52 +[UP] flip: 0, stem: 15912, fault:20. flip_cnt: 0, stem_cnt: 85, fault_cnt:62 +[UP] flip: 22, stem: 3978, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:68 +[UP] flip: 26, stem: 3972, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:63 +[UP] flip: 25, stem: 3972, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:63 +[UP] flip: 20, stem: 3972, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:63 +[UP] flip: 44, stem: 3972, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:64 +[UP] flip: 34, stem: 3972, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:63 +[UP] flip: 29, stem: 3972, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:63 +[UP] flip: 41, stem: 3972, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:63 +[UP] flip: 38, stem: 3972, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:63 +[UP] flip: 135, stem: 3974, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:62 +[UP] flip: 113, stem: 11953, fault:20. flip_cnt: 7, stem_cnt: 92, fault_cnt:109 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 7985, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:37 +[UP] flip: 33, stem: 3992, fault:9. flip_cnt: 12, stem_cnt: 95, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 3, fault:3. flip_cnt: 9, stem_cnt: 93, fault_cnt:89 +[UP] flip: 0, stem: 3996, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:89 +[UP] flip: 13, stem: 15986, fault:20. flip_cnt: 4, stem_cnt: 90, fault_cnt:27 +[UP] flip: 156, stem: 7994, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 19996, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:25 +[UP] flip: 2, stem: 3, fault:4. flip_cnt: 2, stem_cnt: 93, fault_cnt:37 +[UP] flip: 89, stem: 2, fault:10. flip_cnt: 37, stem_cnt: 94, fault_cnt:40 +[UP] flip: 6, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:58 +[UP] flip: 63, stem: 2, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 12016, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:37 +[UP] flip: 16, stem: 16026, fault:9. flip_cnt: 7, stem_cnt: 90, fault_cnt:38 +[UP] flip: 17, stem: 8014, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:50 +[UP] flip: 9, stem: 16029, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:51 +[UP] flip: 0, stem: 16033, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:49 +[UP] flip: 0, stem: 12029, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:20 +[UP] flip: 88, stem: 12025, fault:19. flip_cnt: 15, stem_cnt: 93, fault_cnt:27 +[UP] flip: 112, stem: 3, fault:19. flip_cnt: 19, stem_cnt: 93, fault_cnt:42 +[UP] flip: 109, stem: 2, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:52 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8031, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:67 +[UP] flip: 54, stem: 2, fault:9. flip_cnt: 23, stem_cnt: 94, fault_cnt:33 +[UP] flip: 8, stem: 4019, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:43 +[UP] flip: 10, stem: 8035, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 12063, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:46 +[UP] flip: 6, stem: 4023, fault:9. flip_cnt: 2, stem_cnt: 93, fault_cnt:43 +[UP] flip: 0, stem: 16089, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:33 +[UP] flip: 8, stem: 24135, fault:20. flip_cnt: 2, stem_cnt: 91, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 19, stem: 24151, fault:3. flip_cnt: 11, stem_cnt: 89, fault_cnt:38 +[UP] flip: 3, stem: 16103, fault:10. flip_cnt: 1, stem_cnt: 92, fault_cnt:42 +[UP] flip: 19, stem: 8052, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:47 +[UP] flip: 5, stem: 12078, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:42 +[UP] flip: 0, stem: 8059, fault:24. flip_cnt: 0, stem_cnt: 93, fault_cnt:41 +[UP] flip: 207, stem: 8056, fault:24. flip_cnt: 37, stem_cnt: 93, fault_cnt:33 +[UP] flip: 58, stem: 3, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:50 +[UP] flip: 14, stem: 4033, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:74 +[UP] flip: 117, stem: 1, fault:19. flip_cnt: 15, stem_cnt: 95, fault_cnt:91 +[UP] flip: 163, stem: 1, fault:19. flip_cnt: 19, stem_cnt: 95, fault_cnt:87 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 20181, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:19 +[UP] flip: 77, stem: 8073, fault:9. flip_cnt: 27, stem_cnt: 94, fault_cnt:26 +[UP] flip: 25, stem: 8076, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:56 +[UP] flip: 2, stem: 8075, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:66 +[UP] flip: 20, stem: 1, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:53 +[UP] flip: 42, stem: 4037, fault:20. flip_cnt: 7, stem_cnt: 95, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 16173, fault:3. flip_cnt: 2, stem_cnt: 91, fault_cnt:44 +[UP] flip: 11, stem: 4045, fault:9. flip_cnt: 4, stem_cnt: 94, fault_cnt:47 +[UP] flip: 10, stem: 12134, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:44 +[UP] flip: 88, stem: 4047, fault:20. flip_cnt: 28, stem_cnt: 93, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 28339, fault:3. flip_cnt: 9, stem_cnt: 86, fault_cnt:84 +[UP] flip: 7, stem: 8, fault:10. flip_cnt: 3, stem_cnt: 88, fault_cnt:50 +[UP] flip: 14, stem: 12151, fault:19. flip_cnt: 4, stem_cnt: 92, fault_cnt:55 +[UP] flip: 0, stem: 12152, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:53 +[UP] flip: 55, stem: 8107, fault:19. flip_cnt: 11, stem_cnt: 91, fault_cnt:47 +[UP] flip: 0, stem: 12156, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:54 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 20277, fault:3. flip_cnt: 4, stem_cnt: 89, fault_cnt:37 +[UP] flip: 6, stem: 8112, fault:9. flip_cnt: 2, stem_cnt: 93, fault_cnt:40 +[UP] flip: 31, stem: 8111, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:57 +[UP] flip: 41, stem: 4060, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:29 +[UP] flip: 32, stem: 1, fault:20. flip_cnt: 7, stem_cnt: 95, fault_cnt:54 +[UP] flip: 11, stem: 0, fault:20. flip_cnt: 3, stem_cnt: 96, fault_cnt:57 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 12187, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:30 +[UP] flip: 4, stem: 8128, fault:12. flip_cnt: 2, stem_cnt: 92, fault_cnt:32 +[UP] flip: 28, stem: 2, fault:18. flip_cnt: 8, stem_cnt: 94, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 16267, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:87 +[UP] flip: 4, stem: 12203, fault:9. flip_cnt: 2, stem_cnt: 91, fault_cnt:48 +[UP] flip: 51, stem: 8136, fault:20. flip_cnt: 15, stem_cnt: 93, fault_cnt:60 +[UP] flip: 12, stem: 4070, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:54 +[UP] flip: 12, stem: 4071, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:56 +[UP] flip: 16, stem: 4071, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 20, stem: 4071, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 24, stem: 4071, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 287, stem: 4076, fault:24. flip_cnt: 37, stem_cnt: 93, fault_cnt:37 +[UP] flip: 192, stem: 4070, fault:19. flip_cnt: 20, stem_cnt: 94, fault_cnt:35 +[UP] flip: 88, stem: 2, fault:20. flip_cnt: 9, stem_cnt: 94, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 20392, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:26 +[UP] flip: 7, stem: 8, fault:9. flip_cnt: 3, stem_cnt: 88, fault_cnt:44 +[UP] flip: 15, stem: 8160, fault:20. flip_cnt: 5, stem_cnt: 93, fault_cnt:41 +[UP] flip: 19, stem: 4079, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:56 +[UP] flip: 48, stem: 3, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:48 +[UP] flip: 4, stem: 1, fault:24. flip_cnt: 1, stem_cnt: 95, fault_cnt:85 +[UP] flip: 46, stem: 4081, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:80 +[UP] flip: 106, stem: 2, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:83 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 20437, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:13 +[UP] flip: 59, stem: 8177, fault:9. flip_cnt: 27, stem_cnt: 93, fault_cnt:66 +[UP] flip: 27, stem: 8179, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:76 +[UP] flip: 0, stem: 16358, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:60 +[UP] flip: 47, stem: 1, fault:20. flip_cnt: 11, stem_cnt: 95, fault_cnt:38 +[UP] flip: 67, stem: 1, fault:20. flip_cnt: 15, stem_cnt: 95, fault_cnt:28 +[UP] flip: 86, stem: 1, fault:20. flip_cnt: 13, stem_cnt: 95, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 12286, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 28680, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:49 +[UP] flip: 20, stem: 12293, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:59 +[UP] flip: 39, stem: 8196, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:53 +[UP] flip: 10, stem: 12295, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:56 +[UP] flip: 19, stem: 8203, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:53 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 20518, fault:3. flip_cnt: 9, stem_cnt: 88, fault_cnt:33 +[UP] flip: 15, stem: 16417, fault:9. flip_cnt: 7, stem_cnt: 91, fault_cnt:24 +[UP] flip: 6, stem: 16417, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:42 +[UP] flip: 133, stem: 12316, fault:19. flip_cnt: 37, stem_cnt: 92, fault_cnt:32 +[UP] flip: 10, stem: 16423, fault:19. flip_cnt: 2, stem_cnt: 93, fault_cnt:50 +[UP] flip: 42, stem: 12315, fault:19. flip_cnt: 9, stem_cnt: 92, fault_cnt:58 +[UP] flip: 14, stem: 20522, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:62 +[UP] flip: 0, stem: 16426, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:56 +[UP] flip: 54, stem: 8222, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:62 +[UP] flip: 88, stem: 4113, fault:19. flip_cnt: 11, stem_cnt: 94, fault_cnt:54 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 20572, fault:3. flip_cnt: 4, stem_cnt: 89, fault_cnt:29 +[UP] flip: 8, stem: 8231, fault:9. flip_cnt: 3, stem_cnt: 93, fault_cnt:34 +[UP] flip: 8, stem: 4122, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:45 +[UP] flip: 15, stem: 20584, fault:20. flip_cnt: 4, stem_cnt: 90, fault_cnt:32 +[UP] flip: 30, stem: 8233, fault:20. flip_cnt: 10, stem_cnt: 94, fault_cnt:24 +[UP] flip: 0, stem: 8234, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:46 +[UP] flip: 43, stem: 4115, fault:26. flip_cnt: 10, stem_cnt: 95, fault_cnt:46 +[UP] flip: 6, stem: 1, fault:26. flip_cnt: 1, stem_cnt: 95, fault_cnt:71 +[UP] flip: 98, stem: 4120, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:63 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 12373, fault:3. flip_cnt: 6, stem_cnt: 92, fault_cnt:72 +[UP] flip: 8, stem: 4134, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:41 +[UP] flip: 63, stem: 16506, fault:20. flip_cnt: 19, stem_cnt: 90, fault_cnt:43 +[UP] flip: 12, stem: 12384, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:64 +[UP] flip: 0, stem: 4126, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:72 +[UP] flip: 15, stem: 0, fault:19. flip_cnt: 3, stem_cnt: 96, fault_cnt:72 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 16525, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:21 +[UP] flip: 8, stem: 8271, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:35 +[UP] flip: 0, stem: 4134, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:35 +[UP] flip: 11, stem: 8266, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:27 +[UP] flip: 0, stem: 12401, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:18 +[UP] flip: 34, stem: 20667, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:27 +[UP] flip: 0, stem: 24802, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:31 +[UP] flip: 0, stem: 24809, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:18 +[UP] flip: 0, stem: 28946, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:18 +[UP] flip: 0, stem: 33087, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:18 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 24853, fault:3. flip_cnt: 4, stem_cnt: 89, fault_cnt:24 +[UP] flip: 105, stem: 2, fault:9. flip_cnt: 37, stem_cnt: 94, fault_cnt:46 +[UP] flip: 5, stem: 4145, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:80 +[UP] flip: 43, stem: 4145, fault:19. flip_cnt: 11, stem_cnt: 94, fault_cnt:75 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 11, stem: 12442, fault:3. flip_cnt: 7, stem_cnt: 92, fault_cnt:35 +[UP] flip: 6, stem: 4155, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:51 +[UP] flip: 13, stem: 8300, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:33 +[UP] flip: 12, stem: 8301, fault:19. flip_cnt: 3, stem_cnt: 93, fault_cnt:34 +[UP] flip: 22, stem: 8300, fault:19. flip_cnt: 9, stem_cnt: 92, fault_cnt:41 +[UP] flip: 5, stem: 8303, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:89 +[UP] flip: 14, stem: 12453, fault:19. flip_cnt: 2, stem_cnt: 93, fault_cnt:85 +[UP] flip: 12, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:100 +[UP] flip: 234, stem: 2, fault:20. flip_cnt: 27, stem_cnt: 94, fault_cnt:89 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 20786, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:13 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:21 +[UP] flip: 0, stem: 4160, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:18 +[UP] flip: 33, stem: 8322, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:17 +[UP] flip: 0, stem: 4170, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:20 +[UP] flip: 0, stem: 20809, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:20 +[UP] flip: 2, stem: 8324, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:14 +[UP] flip: 0, stem: 20817, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:14 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 24997, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:36 +[UP] flip: 21, stem: 8333, fault:9. flip_cnt: 9, stem_cnt: 93, fault_cnt:52 +[UP] flip: 78, stem: 8337, fault:20. flip_cnt: 27, stem_cnt: 93, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 12512, fault:3. flip_cnt: 7, stem_cnt: 91, fault_cnt:26 +[UP] flip: 7, stem: 9, fault:10. flip_cnt: 3, stem_cnt: 87, fault_cnt:48 +[UP] flip: 14, stem: 4171, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:36 +[UP] flip: 142, stem: 4175, fault:19. flip_cnt: 37, stem_cnt: 93, fault_cnt:33 +[UP] flip: 16, stem: 4173, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 25, stem: 4173, fault:19. flip_cnt: 5, stem_cnt: 95, fault_cnt:50 +[UP] flip: 13, stem: 4173, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 32, stem: 4173, fault:19. flip_cnt: 5, stem_cnt: 95, fault_cnt:50 +[UP] flip: 8, stem: 4180, fault:19. flip_cnt: 1, stem_cnt: 93, fault_cnt:80 +[UP] flip: 259, stem: 3, fault:19. flip_cnt: 27, stem_cnt: 93, fault_cnt:75 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 10, stem: 20907, fault:3. flip_cnt: 7, stem_cnt: 89, fault_cnt:24 +[UP] flip: 0, stem: 12551, fault:12. flip_cnt: 0, stem_cnt: 86, fault_cnt:35 +[UP] flip: 0, stem: 12547, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:35 +[UP] flip: 41, stem: 1, fault:24. flip_cnt: 10, stem_cnt: 95, fault_cnt:42 +[UP] flip: 140, stem: 2, fault:24. flip_cnt: 37, stem_cnt: 94, fault_cnt:45 +[UP] flip: 7, stem: 1, fault:24. flip_cnt: 1, stem_cnt: 95, fault_cnt:61 +[UP] flip: 55, stem: 2, fault:20. flip_cnt: 8, stem_cnt: 94, fault_cnt:54 +[UP] flip: 138, stem: 4191, fault:20. flip_cnt: 19, stem_cnt: 92, fault_cnt:52 +[UP] flip: 151, stem: 1, fault:19. flip_cnt: 19, stem_cnt: 95, fault_cnt:56 +[UP] flip: 83, stem: 1, fault:19. flip_cnt: 9, stem_cnt: 95, fault_cnt:62 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 16769, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:28 +[UP] flip: 78, stem: 4195, fault:9. flip_cnt: 37, stem_cnt: 93, fault_cnt:36 +[UP] flip: 21, stem: 4192, fault:20. flip_cnt: 7, stem_cnt: 95, fault_cnt:55 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 16785, fault:3. flip_cnt: 4, stem_cnt: 91, fault_cnt:29 +[UP] flip: 14, stem: 4198, fault:9. flip_cnt: 5, stem_cnt: 94, fault_cnt:50 +[UP] flip: 135, stem: 8396, fault:20. flip_cnt: 37, stem_cnt: 92, fault_cnt:41 +[UP] flip: 5, stem: 8395, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 22, stem: 4204, fault:3. flip_cnt: 11, stem_cnt: 92, fault_cnt:35 +[UP] flip: 0, stem: 21011, fault:9. flip_cnt: 0, stem_cnt: 90, fault_cnt:41 +[UP] flip: 4, stem: 4204, fault:23. flip_cnt: 1, stem_cnt: 94, fault_cnt:53 +[UP] flip: 24, stem: 12609, fault:23. flip_cnt: 9, stem_cnt: 92, fault_cnt:52 +[UP] flip: 17, stem: 21014, fault:23. flip_cnt: 3, stem_cnt: 87, fault_cnt:51 +[UP] flip: 20, stem: 21014, fault:23. flip_cnt: 3, stem_cnt: 87, fault_cnt:51 +[UP] flip: 210, stem: 8416, fault:23. flip_cnt: 37, stem_cnt: 92, fault_cnt:33 +[UP] flip: 53, stem: 3, fault:28. flip_cnt: 9, stem_cnt: 93, fault_cnt:47 +[UP] flip: 9, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:88 +[UP] flip: 19, stem: 4211, fault:28. flip_cnt: 2, stem_cnt: 94, fault_cnt:92 +[UP] flip: 21, stem: 8402, fault:28. flip_cnt: 2, stem_cnt: 94, fault_cnt:86 +[UP] flip: 21, stem: 4201, fault:28. flip_cnt: 2, stem_cnt: 94, fault_cnt:86 +[UP] flip: 19, stem: 4201, fault:28. flip_cnt: 2, stem_cnt: 94, fault_cnt:86 +[UP] flip: 23, stem: 4201, fault:28. flip_cnt: 2, stem_cnt: 94, fault_cnt:88 +[UP] flip: 74, stem: 12600, fault:28. flip_cnt: 9, stem_cnt: 93, fault_cnt:83 +[UP] flip: 25, stem: 8401, fault:28. flip_cnt: 2, stem_cnt: 94, fault_cnt:85 +[UP] flip: 88, stem: 8384, fault:28. flip_cnt: 9, stem_cnt: 93, fault_cnt:80 +[UP] flip: 27, stem: 12603, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:96 +[UP] flip: 327, stem: 21036, fault:20. flip_cnt: 19, stem_cnt: 93, fault_cnt:86 +[UP] flip: 11, stem: 21014, fault:20. flip_cnt: 1, stem_cnt: 87, fault_cnt:85 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 8447, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:46 +[UP] flip: 9, stem: 4232, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:57 +[UP] flip: 27, stem: 4226, fault:23. flip_cnt: 7, stem_cnt: 93, fault_cnt:38 +[UP] flip: 13, stem: 8451, fault:23. flip_cnt: 3, stem_cnt: 93, fault_cnt:36 +[UP] flip: 43, stem: 4228, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:49 +[UP] flip: 14, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:55 +[UP] flip: 19, stem: 4223, fault:27. flip_cnt: 3, stem_cnt: 94, fault_cnt:55 +[UP] flip: 28, stem: 8454, fault:27. flip_cnt: 4, stem_cnt: 94, fault_cnt:48 +[UP] flip: 9, stem: 4231, fault:27. flip_cnt: 1, stem_cnt: 94, fault_cnt:88 +[UP] flip: 115, stem: 2, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:84 +[UP] flip: 0, stem: 4233, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:89 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8469, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:31 +[UP] flip: 44, stem: 1, fault:9. flip_cnt: 19, stem_cnt: 95, fault_cnt:39 +[UP] flip: 0, stem: 4238, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:47 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:56 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 4241, fault:3. flip_cnt: 0, stem_cnt: 94, fault_cnt:43 +[UP] flip: 8, stem: 4250, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:41 +[UP] flip: 0, stem: 12727, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:41 +[UP] flip: 0, stem: 12726, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:45 +[UP] flip: 49, stem: 12728, fault:20. flip_cnt: 10, stem_cnt: 94, fault_cnt:28 +[UP] flip: 222, stem: 16973, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:16 +[UP] flip: 0, stem: 12727, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:31 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 21247, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:14 +[UP] flip: 13, stem: 8499, fault:9. flip_cnt: 7, stem_cnt: 94, fault_cnt:41 +[UP] flip: 39, stem: 4252, fault:20. flip_cnt: 15, stem_cnt: 94, fault_cnt:36 +[UP] flip: 35, stem: 1, fault:19. flip_cnt: 9, stem_cnt: 95, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 17017, fault:3. flip_cnt: 3, stem_cnt: 91, fault_cnt:48 +[UP] flip: 37, stem: 8511, fault:9. flip_cnt: 13, stem_cnt: 93, fault_cnt:40 +[UP] flip: 118, stem: 2, fault:20. flip_cnt: 37, stem_cnt: 94, fault_cnt:26 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 8516, fault:3. flip_cnt: 3, stem_cnt: 94, fault_cnt:28 +[UP] flip: 0, stem: 8519, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:48 +[UP] flip: 10, stem: 17039, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:35 +[UP] flip: 33, stem: 8523, fault:19. flip_cnt: 7, stem_cnt: 93, fault_cnt:25 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:44 +[UP] flip: 20, stem: 0, fault:19. flip_cnt: 3, stem_cnt: 96, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 12797, fault:3. flip_cnt: 7, stem_cnt: 91, fault_cnt:26 +[UP] flip: 3, stem: 8534, fault:9. flip_cnt: 1, stem_cnt: 92, fault_cnt:14 +[UP] flip: 10, stem: 12800, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:29 +[UP] flip: 11, stem: 12802, fault:24. flip_cnt: 3, stem_cnt: 93, fault_cnt:53 +[UP] flip: 24, stem: 4266, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:59 +[UP] flip: 13, stem: 4266, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:56 +[UP] flip: 29, stem: 4266, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:60 +[UP] flip: 0, stem: 4272, fault:24. flip_cnt: 0, stem_cnt: 95, fault_cnt:59 +[UP] flip: 21, stem: 4266, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:56 +[UP] flip: 9, stem: 12809, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:64 +[UP] flip: 27, stem: 4266, fault:31. flip_cnt: 4, stem_cnt: 95, fault_cnt:57 +[UP] flip: 44, stem: 4266, fault:31. flip_cnt: 4, stem_cnt: 95, fault_cnt:57 +[UP] flip: 2, stem: 4268, fault:31. flip_cnt: 1, stem_cnt: 94, fault_cnt:90 +[UP] flip: 349, stem: 12813, fault:20. flip_cnt: 27, stem_cnt: 92, fault_cnt:76 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 17121, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 21411, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:77 +[UP] flip: 17, stem: 17131, fault:9. flip_cnt: 6, stem_cnt: 92, fault_cnt:62 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 21428, fault:3. flip_cnt: 9, stem_cnt: 88, fault_cnt:53 +[UP] flip: 5, stem: 17144, fault:9. flip_cnt: 2, stem_cnt: 91, fault_cnt:30 +[UP] flip: 60, stem: 4289, fault:20. flip_cnt: 19, stem_cnt: 93, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 25737, fault:3. flip_cnt: 9, stem_cnt: 87, fault_cnt:52 +[UP] flip: 0, stem: 1, fault:10. flip_cnt: 0, stem_cnt: 95, fault_cnt:54 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 17170, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:23 +[UP] flip: 9, stem: 4294, fault:9. flip_cnt: 3, stem_cnt: 94, fault_cnt:36 +[UP] flip: 10, stem: 12881, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:33 +[UP] flip: 84, stem: 4297, fault:20. flip_cnt: 27, stem_cnt: 92, fault_cnt:49 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 17191, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:27 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:41 +[UP] flip: 0, stem: 4300, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 12904, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:40 +[UP] flip: 11, stem: 4304, fault:12. flip_cnt: 4, stem_cnt: 93, fault_cnt:32 +[UP] flip: 117, stem: 4305, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:33 +[UP] flip: 36, stem: 3, fault:22. flip_cnt: 9, stem_cnt: 93, fault_cnt:44 +[UP] flip: 3, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:83 +[UP] flip: 9, stem: 4307, fault:22. flip_cnt: 2, stem_cnt: 94, fault_cnt:87 +[UP] flip: 11, stem: 2, fault:22. flip_cnt: 2, stem_cnt: 94, fault_cnt:84 +[UP] flip: 63, stem: 4303, fault:22. flip_cnt: 9, stem_cnt: 93, fault_cnt:79 +[UP] flip: 8, stem: 8619, fault:22. flip_cnt: 1, stem_cnt: 86, fault_cnt:89 +[UP] flip: 27, stem: 21534, fault:22. flip_cnt: 3, stem_cnt: 92, fault_cnt:75 +[UP] flip: 281, stem: 3, fault:20. flip_cnt: 30, stem_cnt: 93, fault_cnt:106 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 17261, fault:3. flip_cnt: 0, stem_cnt: 83, fault_cnt:26 +[UP] flip: 6, stem: 12943, fault:9. flip_cnt: 3, stem_cnt: 92, fault_cnt:47 +[UP] flip: 121, stem: 4317, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:27 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 24, stem: 12953, fault:3. flip_cnt: 15, stem_cnt: 91, fault_cnt:67 +[UP] flip: 3, stem: 4319, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:58 +[UP] flip: 47, stem: 8639, fault:20. flip_cnt: 13, stem_cnt: 93, fault_cnt:62 +[UP] flip: 31, stem: 1, fault:19. flip_cnt: 7, stem_cnt: 95, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 8645, fault:3. flip_cnt: 2, stem_cnt: 93, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 21622, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:65 +[UP] flip: 2, stem: 2, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:60 +[UP] flip: 28, stem: 4327, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:55 +[UP] flip: 50, stem: 1, fault:19. flip_cnt: 11, stem_cnt: 95, fault_cnt:65 +[UP] flip: 82, stem: 4330, fault:19. flip_cnt: 15, stem_cnt: 93, fault_cnt:63 +[UP] flip: 97, stem: 4330, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:57 +[UP] flip: 0, stem: 4329, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:68 +[UP] flip: 27, stem: 4328, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:70 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 9, stem: 13000, fault:3. flip_cnt: 5, stem_cnt: 92, fault_cnt:45 +[UP] flip: 3, stem: 4335, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:41 +[UP] flip: 127, stem: 4337, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:39 +[UP] flip: 0, stem: 8671, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 21692, fault:3. flip_cnt: 2, stem_cnt: 89, fault_cnt:25 +[UP] flip: 0, stem: 13019, fault:9. flip_cnt: 0, stem_cnt: 91, fault_cnt:17 +[UP] flip: 87, stem: 4343, fault:24. flip_cnt: 32, stem_cnt: 92, fault_cnt:54 +[UP] flip: 160, stem: 4339, fault:24. flip_cnt: 37, stem_cnt: 94, fault_cnt:56 +[UP] flip: 33, stem: 4341, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:85 +[UP] flip: 71, stem: 2, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:87 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 26071, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:73 +[UP] flip: 5, stem: 21730, fault:9. flip_cnt: 2, stem_cnt: 90, fault_cnt:65 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:56 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 9, stem: 17408, fault:3. flip_cnt: 5, stem_cnt: 84, fault_cnt:64 +[UP] flip: 0, stem: 13054, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:64 +[UP] flip: 11, stem: 13056, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:47 +[UP] flip: 27, stem: 3, fault:19. flip_cnt: 7, stem_cnt: 93, fault_cnt:34 +[UP] flip: 30, stem: 2, fault:19. flip_cnt: 9, stem_cnt: 94, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 13071, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:89 +[UP] flip: 0, stem: 8721, fault:10. flip_cnt: 0, stem_cnt: 86, fault_cnt:64 +[UP] flip: 0, stem: 13075, fault:19. flip_cnt: 0, stem_cnt: 92, fault_cnt:64 +[UP] flip: 0, stem: 8717, fault:23. flip_cnt: 0, stem_cnt: 94, fault_cnt:54 +[UP] flip: 43, stem: 4358, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:53 +[UP] flip: 214, stem: 8718, fault:23. flip_cnt: 37, stem_cnt: 93, fault_cnt:57 +[UP] flip: 57, stem: 2, fault:19. flip_cnt: 8, stem_cnt: 94, fault_cnt:60 +[UP] flip: 122, stem: 2, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:64 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 17461, fault:3. flip_cnt: 8, stem_cnt: 91, fault_cnt:38 +[UP] flip: 0, stem: 13105, fault:9. flip_cnt: 0, stem_cnt: 85, fault_cnt:24 +[UP] flip: 113, stem: 26201, fault:20. flip_cnt: 37, stem_cnt: 89, fault_cnt:14 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8739, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 8743, fault:3. flip_cnt: 3, stem_cnt: 93, fault_cnt:36 +[UP] flip: 4, stem: 4373, fault:9. flip_cnt: 2, stem_cnt: 94, fault_cnt:57 +[UP] flip: 0, stem: 13117, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:50 +[UP] flip: 46, stem: 4375, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:54 +[UP] flip: 0, stem: 13126, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:52 +[UP] flip: 16, stem: 4377, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:62 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 21891, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:46 +[UP] flip: 27, stem: 17515, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:35 +[UP] flip: 13, stem: 21901, fault:20. flip_cnt: 4, stem_cnt: 90, fault_cnt:23 +[UP] flip: 0, stem: 17521, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:48 +[UP] flip: 38, stem: 1, fault:19. flip_cnt: 7, stem_cnt: 95, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 13153, fault:3. flip_cnt: 3, stem_cnt: 92, fault_cnt:42 +[UP] flip: 33, stem: 1, fault:9. flip_cnt: 13, stem_cnt: 95, fault_cnt:43 +[UP] flip: 0, stem: 4387, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:49 +[UP] flip: 6, stem: 4389, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:56 +[UP] flip: 14, stem: 4389, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:53 +[UP] flip: 21, stem: 1, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 63, stem: 4386, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:46 +[UP] flip: 95, stem: 13169, fault:20. flip_cnt: 15, stem_cnt: 92, fault_cnt:51 +[UP] flip: 0, stem: 8784, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 17584, fault:3. flip_cnt: 0, stem_cnt: 84, fault_cnt:17 +[UP] flip: 0, stem: 21974, fault:9. flip_cnt: 0, stem_cnt: 91, fault_cnt:28 +[UP] flip: 5, stem: 17584, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:46 +[UP] flip: 0, stem: 13192, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:31 +[UP] flip: 2, stem: 2, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:24 +[UP] flip: 63, stem: 2, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:24 +[UP] flip: 65, stem: 1, fault:20. flip_cnt: 9, stem_cnt: 95, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 22011, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:42 +[UP] flip: 61, stem: 13209, fault:9. flip_cnt: 24, stem_cnt: 93, fault_cnt:57 +[UP] flip: 10, stem: 8809, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:44 +[UP] flip: 3, stem: 8809, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:41 +[UP] flip: 185, stem: 4406, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 17633, fault:3. flip_cnt: 8, stem_cnt: 91, fault_cnt:48 +[UP] flip: 48, stem: 8818, fault:9. flip_cnt: 19, stem_cnt: 93, fault_cnt:45 +[UP] flip: 4, stem: 8819, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:43 +[UP] flip: 0, stem: 8820, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:46 +[UP] flip: 9, stem: 4410, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 26487, fault:3. flip_cnt: 9, stem_cnt: 87, fault_cnt:73 +[UP] flip: 5, stem: 22076, fault:9. flip_cnt: 3, stem_cnt: 90, fault_cnt:39 +[UP] flip: 11, stem: 26490, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:34 +[UP] flip: 14, stem: 8831, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:50 +[UP] flip: 16, stem: 4414, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 18, stem: 4414, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 15, stem: 4414, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 22, stem: 4414, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 27, stem: 4414, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 13, stem: 1, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 34, stem: 4414, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 32, stem: 4414, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 106, stem: 4417, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:44 +[UP] flip: 82, stem: 8845, fault:19. flip_cnt: 7, stem_cnt: 93, fault_cnt:74 +[UP] flip: 22, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:92 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 17721, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:35 +[UP] flip: 18, stem: 1, fault:9. flip_cnt: 7, stem_cnt: 95, fault_cnt:42 +[UP] flip: 13, stem: 4434, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:54 +[UP] flip: 16, stem: 8864, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:52 +[UP] flip: 0, stem: 13297, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:51 +[UP] flip: 0, stem: 17733, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:50 +[UP] flip: 0, stem: 22166, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:51 +[UP] flip: 0, stem: 26603, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:51 +[UP] flip: 0, stem: 35478, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:51 +[UP] flip: 0, stem: 48793, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:51 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 17765, fault:3. flip_cnt: 6, stem_cnt: 91, fault_cnt:65 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:47 +[UP] flip: 0, stem: 4444, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:41 +[UP] flip: 8, stem: 8884, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 26676, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:24 +[UP] flip: 59, stem: 8897, fault:10. flip_cnt: 27, stem_cnt: 91, fault_cnt:43 +[UP] flip: 0, stem: 1, fault:18. flip_cnt: 0, stem_cnt: 95, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 22252, fault:3. flip_cnt: 4, stem_cnt: 89, fault_cnt:28 +[UP] flip: 8, stem: 8903, fault:10. flip_cnt: 3, stem_cnt: 93, fault_cnt:31 +[UP] flip: 90, stem: 8903, fault:19. flip_cnt: 37, stem_cnt: 93, fault_cnt:30 +[UP] flip: 11, stem: 4452, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 13, stem: 4452, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 14, stem: 4452, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 29, stem: 8908, fault:19. flip_cnt: 5, stem_cnt: 94, fault_cnt:50 +[UP] flip: 14, stem: 4452, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 18, stem: 4452, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 12, stem: 4452, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:53 +[UP] flip: 77, stem: 4452, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:52 +[UP] flip: 12, stem: 8913, fault:19. flip_cnt: 1, stem_cnt: 93, fault_cnt:60 +[UP] flip: 0, stem: 13374, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:50 +[UP] flip: 0, stem: 4456, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:59 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 17860, fault:3. flip_cnt: 3, stem_cnt: 92, fault_cnt:46 +[UP] flip: 3, stem: 13405, fault:9. flip_cnt: 3, stem_cnt: 85, fault_cnt:58 +[UP] flip: 36, stem: 13402, fault:20. flip_cnt: 11, stem_cnt: 92, fault_cnt:58 +[UP] flip: 11, stem: 8935, fault:19. flip_cnt: 5, stem_cnt: 94, fault_cnt:41 +[UP] flip: 22, stem: 4469, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 26827, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:38 +[UP] flip: 16, stem: 13415, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:43 +[UP] flip: 8, stem: 8952, fault:20. flip_cnt: 3, stem_cnt: 86, fault_cnt:37 +[UP] flip: 29, stem: 17896, fault:20. flip_cnt: 7, stem_cnt: 91, fault_cnt:23 +[UP] flip: 182, stem: 4477, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:35 +[UP] flip: 14, stem: 4471, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 17, stem: 4471, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 17, stem: 4471, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 23, stem: 4471, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 16, stem: 4471, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 52, stem: 4471, fault:26. flip_cnt: 5, stem_cnt: 95, fault_cnt:58 +[UP] flip: 58, stem: 4471, fault:26. flip_cnt: 5, stem_cnt: 95, fault_cnt:57 +[UP] flip: 95, stem: 8944, fault:26. flip_cnt: 9, stem_cnt: 93, fault_cnt:53 +[UP] flip: 12, stem: 13429, fault:26. flip_cnt: 1, stem_cnt: 94, fault_cnt:63 +[UP] flip: 95, stem: 17904, fault:20. flip_cnt: 7, stem_cnt: 92, fault_cnt:93 +[UP] flip: 5, stem: 22389, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:93 +[UP] flip: 12, stem: 13440, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:94 +[UP] flip: 0, stem: 17916, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:95 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 17961, fault:3. flip_cnt: 1, stem_cnt: 91, fault_cnt:25 +[UP] flip: 13, stem: 8981, fault:10. flip_cnt: 5, stem_cnt: 94, fault_cnt:48 +[UP] flip: 0, stem: 4493, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:44 +[UP] flip: 33, stem: 8985, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 26973, fault:3. flip_cnt: 9, stem_cnt: 87, fault_cnt:14 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 8995, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:39 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:27 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 18002, fault:3. flip_cnt: 1, stem_cnt: 90, fault_cnt:17 +[UP] flip: 25, stem: 13504, fault:9. flip_cnt: 11, stem_cnt: 92, fault_cnt:18 +[UP] flip: 12, stem: 9006, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:20 +[UP] flip: 151, stem: 4505, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:37 +[UP] flip: 21, stem: 4500, fault:20. flip_cnt: 5, stem_cnt: 95, fault_cnt:60 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 27037, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:32 +[UP] flip: 0, stem: 8, fault:12. flip_cnt: 0, stem_cnt: 88, fault_cnt:39 +[UP] flip: 24, stem: 4509, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:49 +[UP] flip: 17, stem: 4508, fault:22. flip_cnt: 5, stem_cnt: 95, fault_cnt:49 +[UP] flip: 14, stem: 4511, fault:22. flip_cnt: 3, stem_cnt: 94, fault_cnt:39 +[UP] flip: 36, stem: 4511, fault:22. flip_cnt: 7, stem_cnt: 94, fault_cnt:40 +[UP] flip: 53, stem: 4515, fault:22. flip_cnt: 9, stem_cnt: 92, fault_cnt:47 +[UP] flip: 15, stem: 4507, fault:22. flip_cnt: 2, stem_cnt: 94, fault_cnt:87 +[UP] flip: 17, stem: 4507, fault:22. flip_cnt: 2, stem_cnt: 94, fault_cnt:88 +[UP] flip: 18, stem: 4507, fault:22. flip_cnt: 2, stem_cnt: 94, fault_cnt:88 +[UP] flip: 20, stem: 4507, fault:22. flip_cnt: 2, stem_cnt: 94, fault_cnt:88 +[UP] flip: 18, stem: 4507, fault:22. flip_cnt: 2, stem_cnt: 94, fault_cnt:88 +[UP] flip: 87, stem: 9014, fault:22. flip_cnt: 9, stem_cnt: 93, fault_cnt:83 +[UP] flip: 12, stem: 22553, fault:22. flip_cnt: 1, stem_cnt: 86, fault_cnt:91 +[UP] flip: 102, stem: 18065, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:91 +[UP] flip: 392, stem: 31595, fault:20. flip_cnt: 27, stem_cnt: 92, fault_cnt:100 +[UP] flip: 40, stem: 22586, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:71 +[UP] flip: 150, stem: 18062, fault:20. flip_cnt: 10, stem_cnt: 93, fault_cnt:63 +[UP] flip: 6, stem: 4520, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:54 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 13579, fault:3. flip_cnt: 2, stem_cnt: 92, fault_cnt:47 +[UP] flip: 9, stem: 13582, fault:12. flip_cnt: 4, stem_cnt: 92, fault_cnt:55 +[UP] flip: 24, stem: 2, fault:18. flip_cnt: 7, stem_cnt: 94, fault_cnt:70 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 9061, fault:3. flip_cnt: 2, stem_cnt: 93, fault_cnt:39 +[UP] flip: 5, stem: 4532, fault:9. flip_cnt: 3, stem_cnt: 94, fault_cnt:44 +[UP] flip: 97, stem: 4534, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 9070, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:42 +[UP] flip: 8, stem: 18139, fault:9. flip_cnt: 3, stem_cnt: 92, fault_cnt:38 +[UP] flip: 0, stem: 9078, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:40 +[UP] flip: 0, stem: 18149, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:43 +[UP] flip: 0, stem: 9077, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:41 +[UP] flip: 47, stem: 4540, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:28 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 22707, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:13 +[UP] flip: 17, stem: 3, fault:9. flip_cnt: 7, stem_cnt: 93, fault_cnt:34 +[UP] flip: 7, stem: 1, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 19, stem: 2, fault:23. flip_cnt: 4, stem_cnt: 94, fault_cnt:37 +[UP] flip: 152, stem: 9087, fault:23. flip_cnt: 37, stem_cnt: 93, fault_cnt:35 +[UP] flip: 45, stem: 4543, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 41, stem: 13643, fault:20. flip_cnt: 7, stem_cnt: 91, fault_cnt:60 +[UP] flip: 72, stem: 4549, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:70 +[UP] flip: 55, stem: 0, fault:19. flip_cnt: 7, stem_cnt: 96, fault_cnt:77 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9111, fault:3. flip_cnt: 0, stem_cnt: 85, fault_cnt:17 +[UP] flip: 20, stem: 9105, fault:9. flip_cnt: 7, stem_cnt: 93, fault_cnt:39 +[UP] flip: 0, stem: 9105, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:37 +[UP] flip: 18, stem: 4554, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 11, stem: 27338, fault:3. flip_cnt: 6, stem_cnt: 88, fault_cnt:27 +[UP] flip: 91, stem: 4559, fault:9. flip_cnt: 37, stem_cnt: 93, fault_cnt:29 +[UP] flip: 4, stem: 4559, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:15 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 22801, fault:3. flip_cnt: 2, stem_cnt: 90, fault_cnt:30 +[UP] flip: 0, stem: 9123, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:39 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:40 +[UP] flip: 19, stem: 0, fault:20. flip_cnt: 4, stem_cnt: 96, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9131, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:36 +[UP] flip: 1, stem: 4567, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:31 +[UP] flip: 37, stem: 4569, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:28 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 18277, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:82 +[UP] flip: 18, stem: 18281, fault:9. flip_cnt: 6, stem_cnt: 91, fault_cnt:33 +[UP] flip: 64, stem: 4573, fault:20. flip_cnt: 19, stem_cnt: 93, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 52, stem: 9148, fault:3. flip_cnt: 37, stem_cnt: 92, fault_cnt:19 +[UP] flip: 7, stem: 9, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:38 +[UP] flip: 0, stem: 13726, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:33 +[UP] flip: 21, stem: 4575, fault:20. flip_cnt: 5, stem_cnt: 95, fault_cnt:47 +[UP] flip: 33, stem: 4574, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:38 +[UP] flip: 47, stem: 2, fault:20. flip_cnt: 9, stem_cnt: 94, fault_cnt:49 +[UP] flip: 6, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:59 +[UP] flip: 182, stem: 4578, fault:20. flip_cnt: 27, stem_cnt: 92, fault_cnt:46 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:52 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 22916, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:14 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:35 +[UP] flip: 0, stem: 4586, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:32 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 13764, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:73 +[UP] flip: 0, stem: 9177, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:79 +[UP] flip: 34, stem: 27531, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:22 +[UP] flip: 7, stem: 4591, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:77 +[UP] flip: 9, stem: 4590, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:79 +[UP] flip: 4, stem: 4592, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:79 +[UP] flip: 23, stem: 2, fault:19. flip_cnt: 4, stem_cnt: 94, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 18382, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:32 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:34 +[UP] flip: 0, stem: 4598, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:18 +[UP] flip: 0, stem: 9194, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:18 +[UP] flip: 0, stem: 13792, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:18 +[UP] flip: 0, stem: 22987, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:18 +[UP] flip: 0, stem: 22992, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:18 +[UP] flip: 0, stem: 27592, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:18 +[UP] flip: 0, stem: 32197, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:18 +[UP] flip: 67, stem: 41403, fault:20. flip_cnt: 7, stem_cnt: 92, fault_cnt:27 +[UP] flip: 0, stem: 36799, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:17 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 27644, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:67 +[UP] flip: 9, stem: 4609, fault:9. flip_cnt: 4, stem_cnt: 94, fault_cnt:35 +[UP] flip: 0, stem: 9219, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:31 +[UP] flip: 105, stem: 4611, fault:20. flip_cnt: 28, stem_cnt: 93, fault_cnt:40 +[UP] flip: 171, stem: 2, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9227, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:43 +[UP] flip: 0, stem: 4615, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:48 +[UP] flip: 0, stem: 4617, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:48 +[UP] flip: 18, stem: 9230, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:41 +[UP] flip: 0, stem: 18469, fault:20. flip_cnt: 0, stem_cnt: 85, fault_cnt:39 +[UP] flip: 0, stem: 36931, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:35 +[UP] flip: 22, stem: 9232, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:36 +[UP] flip: 18, stem: 13851, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:36 +[UP] flip: 13, stem: 13851, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:34 +[UP] flip: 23, stem: 18472, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:34 +[UP] flip: 46, stem: 13862, fault:19. flip_cnt: 9, stem_cnt: 92, fault_cnt:41 +[UP] flip: 0, stem: 23102, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:40 +[UP] flip: 178, stem: 18466, fault:19. flip_cnt: 19, stem_cnt: 92, fault_cnt:41 +[UP] flip: 53, stem: 4613, fault:34. flip_cnt: 5, stem_cnt: 95, fault_cnt:53 +[UP] flip: 37, stem: 4613, fault:34. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 11, stem: 1, fault:34. flip_cnt: 1, stem_cnt: 95, fault_cnt:93 +[UP] flip: 138, stem: 4586, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:85 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9263, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:40 +[UP] flip: 8, stem: 23159, fault:9. flip_cnt: 3, stem_cnt: 91, fault_cnt:40 +[UP] flip: 16, stem: 4639, fault:20. flip_cnt: 5, stem_cnt: 87, fault_cnt:63 +[UP] flip: 9, stem: 4631, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:40 +[UP] flip: 9, stem: 4632, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 18549, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:60 +[UP] flip: 20, stem: 1, fault:9. flip_cnt: 7, stem_cnt: 95, fault_cnt:39 +[UP] flip: 0, stem: 4639, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:42 +[UP] flip: 10, stem: 9279, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:39 +[UP] flip: 13, stem: 23200, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:41 +[UP] flip: 14, stem: 4642, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 13935, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:40 +[UP] flip: 6, stem: 18583, fault:10. flip_cnt: 2, stem_cnt: 89, fault_cnt:23 +[UP] flip: 71, stem: 13939, fault:19. flip_cnt: 23, stem_cnt: 92, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 11, stem: 13947, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:82 +[UP] flip: 91, stem: 4651, fault:9. flip_cnt: 37, stem_cnt: 93, fault_cnt:31 +[UP] flip: 0, stem: 9301, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:17 +[UP] flip: 10, stem: 2, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:28 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 13961, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:33 +[UP] flip: 3, stem: 2, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:37 +[UP] flip: 52, stem: 4657, fault:20. flip_cnt: 19, stem_cnt: 93, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 27943, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:31 +[UP] flip: 12, stem: 9, fault:9. flip_cnt: 5, stem_cnt: 87, fault_cnt:57 +[UP] flip: 16, stem: 4660, fault:20. flip_cnt: 5, stem_cnt: 94, fault_cnt:32 +[UP] flip: 0, stem: 9318, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:31 +[UP] flip: 3, stem: 13981, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:24 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 4664, fault:3. flip_cnt: 4, stem_cnt: 94, fault_cnt:38 +[UP] flip: 6, stem: 4665, fault:9. flip_cnt: 2, stem_cnt: 94, fault_cnt:35 +[UP] flip: 0, stem: 18661, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:35 +[UP] flip: 38, stem: 9333, fault:19. flip_cnt: 10, stem_cnt: 93, fault_cnt:32 +[UP] flip: 0, stem: 4667, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 18679, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:45 +[UP] flip: 17, stem: 9339, fault:9. flip_cnt: 9, stem_cnt: 93, fault_cnt:57 +[UP] flip: 17, stem: 1, fault:20. flip_cnt: 5, stem_cnt: 95, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 23366, fault:3. flip_cnt: 4, stem_cnt: 90, fault_cnt:35 +[UP] flip: 28, stem: 1, fault:9. flip_cnt: 10, stem_cnt: 95, fault_cnt:37 +[UP] flip: 0, stem: 4676, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:46 +[UP] flip: 0, stem: 9350, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:46 +[UP] flip: 0, stem: 14027, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 28075, fault:3. flip_cnt: 4, stem_cnt: 89, fault_cnt:34 +[UP] flip: 20, stem: 23401, fault:9. flip_cnt: 9, stem_cnt: 89, fault_cnt:33 +[UP] flip: 20, stem: 23405, fault:20. flip_cnt: 7, stem_cnt: 86, fault_cnt:88 +[UP] flip: 16, stem: 14044, fault:19. flip_cnt: 4, stem_cnt: 93, fault_cnt:72 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 37473, fault:3. flip_cnt: 0, stem_cnt: 87, fault_cnt:32 +[UP] flip: 24, stem: 9371, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:38 +[UP] flip: 90, stem: 2, fault:20. flip_cnt: 28, stem_cnt: 94, fault_cnt:72 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 9377, fault:3. flip_cnt: 7, stem_cnt: 93, fault_cnt:23 +[UP] flip: 0, stem: 4690, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:38 +[UP] flip: 8, stem: 9386, fault:20. flip_cnt: 3, stem_cnt: 86, fault_cnt:33 +[UP] flip: 0, stem: 28145, fault:20. flip_cnt: 0, stem_cnt: 90, fault_cnt:31 +[UP] flip: 84, stem: 14074, fault:20. flip_cnt: 19, stem_cnt: 92, fault_cnt:15 +[UP] flip: 76, stem: 2, fault:19. flip_cnt: 19, stem_cnt: 94, fault_cnt:26 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 37561, fault:3. flip_cnt: 4, stem_cnt: 87, fault_cnt:34 +[UP] flip: 30, stem: 1, fault:9. flip_cnt: 11, stem_cnt: 95, fault_cnt:52 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 18793, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:66 +[UP] flip: 0, stem: 9399, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:70 +[UP] flip: 12, stem: 9401, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:30 +[UP] flip: 14, stem: 9399, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 14110, fault:3. flip_cnt: 3, stem_cnt: 92, fault_cnt:30 +[UP] flip: 4, stem: 9410, fault:9. flip_cnt: 2, stem_cnt: 92, fault_cnt:34 +[UP] flip: 18, stem: 9411, fault:20. flip_cnt: 5, stem_cnt: 93, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 9416, fault:3. flip_cnt: 4, stem_cnt: 92, fault_cnt:22 +[UP] flip: 0, stem: 14131, fault:9. flip_cnt: 0, stem_cnt: 85, fault_cnt:23 +[UP] flip: 0, stem: 9419, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:31 +[UP] flip: 0, stem: 4711, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:40 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 58, stem: 18854, fault:3. flip_cnt: 37, stem_cnt: 90, fault_cnt:28 +[UP] flip: 67, stem: 14144, fault:9. flip_cnt: 23, stem_cnt: 91, fault_cnt:21 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 2, fault:3. flip_cnt: 9, stem_cnt: 94, fault_cnt:20 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:21 +[UP] flip: 0, stem: 4719, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:18 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 18881, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:72 +[UP] flip: 3, stem: 14165, fault:9. flip_cnt: 1, stem_cnt: 91, fault_cnt:63 +[UP] flip: 7, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:78 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 23622, fault:3. flip_cnt: 4, stem_cnt: 89, fault_cnt:32 +[UP] flip: 12, stem: 9450, fault:9. flip_cnt: 4, stem_cnt: 94, fault_cnt:48 +[UP] flip: 10, stem: 4725, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 11, stem: 4725, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 17, stem: 4725, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 12, stem: 4725, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 19, stem: 4725, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 22, stem: 4725, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 20, stem: 4725, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 37, stem: 4725, fault:23. flip_cnt: 5, stem_cnt: 95, fault_cnt:49 +[UP] flip: 19, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:79 +[UP] flip: 4, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:79 +[UP] flip: 0, stem: 4736, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:79 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 23692, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:18 +[UP] flip: 3, stem: 4741, fault:9. flip_cnt: 1, stem_cnt: 93, fault_cnt:20 +[UP] flip: 25, stem: 14217, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:16 +[UP] flip: 33, stem: 18965, fault:20. flip_cnt: 7, stem_cnt: 91, fault_cnt:34 +[UP] flip: 0, stem: 23709, fault:20. flip_cnt: 0, stem_cnt: 87, fault_cnt:24 +[UP] flip: 0, stem: 18970, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:24 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:24 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 14247, fault:3. flip_cnt: 0, stem_cnt: 84, fault_cnt:25 +[UP] flip: 19, stem: 14242, fault:10. flip_cnt: 7, stem_cnt: 92, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 14250, fault:4. flip_cnt: 9, stem_cnt: 90, fault_cnt:66 +[UP] flip: 0, stem: 9, fault:10. flip_cnt: 0, stem_cnt: 87, fault_cnt:60 +[UP] flip: 0, stem: 14254, fault:17. flip_cnt: 0, stem_cnt: 92, fault_cnt:54 +[UP] flip: 0, stem: 9503, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:67 +[UP] flip: 60, stem: 1, fault:20. flip_cnt: 12, stem_cnt: 95, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 1, stem: 5, fault:0. flip_cnt: 1, stem_cnt: 91, fault_cnt:59 +[UP] flip: 1, stem: 4759, fault:3. flip_cnt: 1, stem_cnt: 92, fault_cnt:49 +[UP] flip: 43, stem: 4759, fault:10. flip_cnt: 15, stem_cnt: 93, fault_cnt:54 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:68 +[UP] flip: 14, stem: 1, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:70 +[UP] flip: 59, stem: 1, fault:19. flip_cnt: 10, stem_cnt: 95, fault_cnt:51 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 23814, fault:3. flip_cnt: 0, stem_cnt: 87, fault_cnt:57 +[UP] flip: 0, stem: 14290, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:38 +[UP] flip: 8, stem: 4763, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:54 +[UP] flip: 14, stem: 4762, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 14, stem: 4762, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 18, stem: 4762, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 15, stem: 4762, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 34, stem: 4762, fault:23. flip_cnt: 5, stem_cnt: 95, fault_cnt:48 +[UP] flip: 20, stem: 4762, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 22, stem: 4762, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 30, stem: 4762, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 106, stem: 4765, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:43 +[UP] flip: 1, stem: 2, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:86 +[UP] flip: 135, stem: 4777, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:81 +[UP] flip: 0, stem: 9538, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:91 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9557, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:35 +[UP] flip: 6, stem: 4781, fault:9. flip_cnt: 2, stem_cnt: 93, fault_cnt:43 +[UP] flip: 0, stem: 4782, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:34 +[UP] flip: 0, stem: 9560, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:34 +[UP] flip: 0, stem: 14342, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:34 +[UP] flip: 0, stem: 19123, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:34 +[UP] flip: 64, stem: 23908, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:33 +[UP] flip: 73, stem: 4781, fault:28. flip_cnt: 10, stem_cnt: 95, fault_cnt:43 +[UP] flip: 3, stem: 1, fault:28. flip_cnt: 1, stem_cnt: 95, fault_cnt:63 +[UP] flip: 105, stem: 9551, fault:20. flip_cnt: 12, stem_cnt: 94, fault_cnt:54 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 23951, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:39 +[UP] flip: 0, stem: 4792, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:34 +[UP] flip: 0, stem: 9584, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 4797, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:40 +[UP] flip: 0, stem: 9599, fault:9. flip_cnt: 0, stem_cnt: 85, fault_cnt:24 +[UP] flip: 0, stem: 19185, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:27 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 19195, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:46 +[UP] flip: 6, stem: 4801, fault:9. flip_cnt: 2, stem_cnt: 93, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 54, stem: 9604, fault:3. flip_cnt: 37, stem_cnt: 92, fault_cnt:32 +[UP] flip: 0, stem: 4803, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:86 +[UP] flip: 104, stem: 9606, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:39 +[UP] flip: 4, stem: 9608, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 24031, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:70 +[UP] flip: 14, stem: 28843, fault:9. flip_cnt: 5, stem_cnt: 89, fault_cnt:39 +[UP] flip: 9, stem: 9617, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:42 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:51 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 33678, fault:3. flip_cnt: 9, stem_cnt: 88, fault_cnt:25 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:3. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 9629, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:41 +[UP] flip: 5, stem: 9628, fault:9. flip_cnt: 3, stem_cnt: 94, fault_cnt:34 +[UP] flip: 0, stem: 4816, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:57 +[UP] flip: 37, stem: 9632, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:50 +[UP] flip: 0, stem: 4816, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:60 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 19277, fault:3. flip_cnt: 3, stem_cnt: 91, fault_cnt:22 +[UP] flip: 0, stem: 4, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:33 +[UP] flip: 40, stem: 4823, fault:9. flip_cnt: 15, stem_cnt: 93, fault_cnt:33 +[UP] flip: 18, stem: 4821, fault:23. flip_cnt: 5, stem_cnt: 95, fault_cnt:50 +[UP] flip: 12, stem: 4821, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 22, stem: 4821, fault:23. flip_cnt: 5, stem_cnt: 95, fault_cnt:49 +[UP] flip: 15, stem: 4821, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 0, stem: 4826, fault:23. flip_cnt: 0, stem_cnt: 95, fault_cnt:49 +[UP] flip: 0, stem: 9652, fault:23. flip_cnt: 0, stem_cnt: 95, fault_cnt:49 +[UP] flip: 24, stem: 4821, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 48, stem: 4821, fault:23. flip_cnt: 5, stem_cnt: 95, fault_cnt:49 +[UP] flip: 24, stem: 4821, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 26, stem: 4821, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 10, stem: 4835, fault:23. flip_cnt: 1, stem_cnt: 92, fault_cnt:86 +[UP] flip: 1, stem: 2, fault:23. flip_cnt: 1, stem_cnt: 94, fault_cnt:90 +[UP] flip: 156, stem: 4836, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:82 +[UP] flip: 26, stem: 4836, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:94 +[UP] flip: 28, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:97 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 29, stem: 29029, fault:3. flip_cnt: 15, stem_cnt: 89, fault_cnt:28 +[UP] flip: 21, stem: 9677, fault:10. flip_cnt: 7, stem_cnt: 94, fault_cnt:38 +[UP] flip: 39, stem: 2, fault:19. flip_cnt: 11, stem_cnt: 94, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 24211, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:41 +[UP] flip: 19, stem: 0, fault:9. flip_cnt: 7, stem_cnt: 96, fault_cnt:64 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9691, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:22 +[UP] flip: 3, stem: 4847, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:18 +[UP] flip: 24, stem: 19389, fault:20. flip_cnt: 7, stem_cnt: 91, fault_cnt:25 +[UP] flip: 0, stem: 9694, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:22 +[UP] flip: 41, stem: 14546, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:21 +[UP] flip: 45, stem: 9695, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:38 +[UP] flip: 76, stem: 14545, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:18 +[UP] flip: 32, stem: 19395, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:18 +[UP] flip: 0, stem: 29094, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:15 +[UP] flip: 0, stem: 9701, fault:30. flip_cnt: 0, stem_cnt: 94, fault_cnt:35 +[UP] flip: 348, stem: 2, fault:30. flip_cnt: 37, stem_cnt: 94, fault_cnt:47 +[UP] flip: 3, stem: 4854, fault:30. flip_cnt: 1, stem_cnt: 95, fault_cnt:64 +[UP] flip: 26, stem: 4850, fault:30. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 66, stem: 4850, fault:30. flip_cnt: 5, stem_cnt: 95, fault_cnt:55 +[UP] flip: 28, stem: 4850, fault:30. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 32, stem: 4850, fault:30. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 42, stem: 4850, fault:30. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 45, stem: 4850, fault:30. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 61, stem: 4850, fault:30. flip_cnt: 5, stem_cnt: 95, fault_cnt:55 +[UP] flip: 44, stem: 4850, fault:30. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 149, stem: 4852, fault:30. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 20, stem: 9722, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:65 +[UP] flip: 147, stem: 24271, fault:20. flip_cnt: 7, stem_cnt: 91, fault_cnt:89 +[UP] flip: 283, stem: 9721, fault:19. flip_cnt: 15, stem_cnt: 93, fault_cnt:85 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 19481, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:41 +[UP] flip: 9, stem: 19483, fault:9. flip_cnt: 3, stem_cnt: 92, fault_cnt:55 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 4, fault:0. flip_cnt: 3, stem_cnt: 92, fault_cnt:14 +[UP] flip: 17, stem: 14625, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:13 +[UP] flip: 16, stem: 9759, fault:9. flip_cnt: 7, stem_cnt: 85, fault_cnt:109 +[UP] flip: 7, stem: 24381, fault:23. flip_cnt: 2, stem_cnt: 90, fault_cnt:74 +[UP] flip: 8, stem: 9750, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:87 +[UP] flip: 9, stem: 4875, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:87 +[UP] flip: 4, stem: 4875, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:87 +[UP] flip: 11, stem: 4875, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:87 +[UP] flip: 5, stem: 4875, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:85 +[UP] flip: 18, stem: 4875, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:86 +[UP] flip: 18, stem: 4875, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:86 +[UP] flip: 79, stem: 4877, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:82 +[UP] flip: 7, stem: 24389, fault:20. flip_cnt: 1, stem_cnt: 90, fault_cnt:86 +[UP] flip: 1, stem: 29274, fault:20. flip_cnt: 1, stem_cnt: 90, fault_cnt:86 +[UP] flip: 188, stem: 4888, fault:20. flip_cnt: 15, stem_cnt: 94, fault_cnt:102 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 20, stem: 34223, fault:3. flip_cnt: 10, stem_cnt: 89, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 14674, fault:3. flip_cnt: 2, stem_cnt: 92, fault_cnt:30 +[UP] flip: 33, stem: 4894, fault:9. flip_cnt: 15, stem_cnt: 93, fault_cnt:43 +[UP] flip: 0, stem: 4894, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:43 +[UP] flip: 13, stem: 4893, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:43 +[UP] flip: 19, stem: 4892, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:32 +[UP] flip: 218, stem: 9788, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:29 +[UP] flip: 19, stem: 4896, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 15, stem: 4896, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 21, stem: 4896, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 25, stem: 4896, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 0, stem: 4901, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:86 +[UP] flip: 266, stem: 4906, fault:20. flip_cnt: 27, stem_cnt: 91, fault_cnt:74 +[UP] flip: 21, stem: 4904, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:72 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 24528, fault:3. flip_cnt: 9, stem_cnt: 88, fault_cnt:35 +[UP] flip: 8, stem: 9821, fault:9. flip_cnt: 3, stem_cnt: 85, fault_cnt:44 +[UP] flip: 13, stem: 19630, fault:20. flip_cnt: 4, stem_cnt: 90, fault_cnt:27 +[UP] flip: 163, stem: 14726, fault:20. flip_cnt: 37, stem_cnt: 91, fault_cnt:29 +[UP] flip: 17, stem: 14726, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 14734, fault:3. flip_cnt: 1, stem_cnt: 92, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 9827, fault:3. flip_cnt: 4, stem_cnt: 93, fault_cnt:48 +[UP] flip: 88, stem: 2, fault:12. flip_cnt: 37, stem_cnt: 94, fault_cnt:37 +[UP] flip: 3, stem: 2, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:54 +[UP] flip: 129, stem: 4919, fault:20. flip_cnt: 28, stem_cnt: 92, fault_cnt:39 +[UP] flip: 12, stem: 14752, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:49 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:53 +[UP] flip: 20, stem: 0, fault:19. flip_cnt: 3, stem_cnt: 96, fault_cnt:52 +[UP] flip: 23, stem: 4921, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:47 +[UP] flip: 74, stem: 19672, fault:19. flip_cnt: 9, stem_cnt: 91, fault_cnt:39 +[UP] flip: 8, stem: 9836, fault:27. flip_cnt: 1, stem_cnt: 94, fault_cnt:51 +[UP] flip: 333, stem: 14760, fault:27. flip_cnt: 37, stem_cnt: 93, fault_cnt:50 +[UP] flip: 206, stem: 4918, fault:20. flip_cnt: 20, stem_cnt: 94, fault_cnt:49 +[UP] flip: 102, stem: 2, fault:19. flip_cnt: 9, stem_cnt: 94, fault_cnt:54 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 19709, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:37 +[UP] flip: 3, stem: 4929, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:27 +[UP] flip: 9, stem: 9864, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:33 +[UP] flip: 147, stem: 9862, fault:24. flip_cnt: 37, stem_cnt: 92, fault_cnt:42 +[UP] flip: 6, stem: 4933, fault:24. flip_cnt: 2, stem_cnt: 93, fault_cnt:51 +[UP] flip: 2, stem: 4930, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:51 +[UP] flip: 75, stem: 4930, fault:20. flip_cnt: 15, stem_cnt: 94, fault_cnt:52 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 19742, fault:3. flip_cnt: 7, stem_cnt: 90, fault_cnt:32 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 29623, fault:3. flip_cnt: 3, stem_cnt: 89, fault_cnt:28 +[UP] flip: 14, stem: 4, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:43 +[UP] flip: 0, stem: 9880, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:61 +[UP] flip: 7, stem: 14819, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 29653, fault:3. flip_cnt: 2, stem_cnt: 89, fault_cnt:24 +[UP] flip: 18, stem: 2, fault:10. flip_cnt: 7, stem_cnt: 94, fault_cnt:45 +[UP] flip: 45, stem: 2, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 19785, fault:3. flip_cnt: 2, stem_cnt: 91, fault_cnt:28 +[UP] flip: 8, stem: 1, fault:11. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 28, stem: 4950, fault:19. flip_cnt: 7, stem_cnt: 93, fault_cnt:36 +[UP] flip: 8, stem: 9897, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 60, stem: 9904, fault:3. flip_cnt: 37, stem_cnt: 92, fault_cnt:20 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 19813, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:45 +[UP] flip: 11, stem: 2, fault:12. flip_cnt: 4, stem_cnt: 94, fault_cnt:38 +[UP] flip: 9, stem: 4956, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:36 +[UP] flip: 38, stem: 3, fault:22. flip_cnt: 9, stem_cnt: 93, fault_cnt:47 +[UP] flip: 6, stem: 1, fault:22. flip_cnt: 1, stem_cnt: 95, fault_cnt:85 +[UP] flip: 40, stem: 2, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:80 +[UP] flip: 105, stem: 4961, fault:20. flip_cnt: 15, stem_cnt: 93, fault_cnt:73 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 41, stem: 24806, fault:3. flip_cnt: 23, stem_cnt: 90, fault_cnt:45 +[UP] flip: 0, stem: 9933, fault:9. flip_cnt: 0, stem_cnt: 85, fault_cnt:43 +[UP] flip: 28, stem: 14888, fault:20. flip_cnt: 7, stem_cnt: 92, fault_cnt:50 +[UP] flip: 51, stem: 9926, fault:19. flip_cnt: 11, stem_cnt: 93, fault_cnt:46 +[UP] flip: 55, stem: 4966, fault:19. flip_cnt: 11, stem_cnt: 94, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 19869, fault:3. flip_cnt: 7, stem_cnt: 91, fault_cnt:63 +[UP] flip: 37, stem: 2, fault:9. flip_cnt: 20, stem_cnt: 94, fault_cnt:57 +[UP] flip: 10, stem: 1, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 44, stem: 4969, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:50 +[UP] flip: 5, stem: 2, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:88 +[UP] flip: 1, stem: 2, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:88 +[UP] flip: 13, stem: 4974, fault:27. flip_cnt: 2, stem_cnt: 94, fault_cnt:93 +[UP] flip: 15, stem: 4968, fault:27. flip_cnt: 2, stem_cnt: 94, fault_cnt:90 +[UP] flip: 58, stem: 3, fault:27. flip_cnt: 9, stem_cnt: 93, fault_cnt:85 +[UP] flip: 7, stem: 14919, fault:20. flip_cnt: 1, stem_cnt: 90, fault_cnt:87 +[UP] flip: 70, stem: 24875, fault:20. flip_cnt: 7, stem_cnt: 91, fault_cnt:102 +[UP] flip: 96, stem: 2, fault:19. flip_cnt: 9, stem_cnt: 94, fault_cnt:109 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 19921, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:31 +[UP] flip: 4, stem: 19923, fault:9. flip_cnt: 2, stem_cnt: 92, fault_cnt:37 +[UP] flip: 0, stem: 9965, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:34 +[UP] flip: 31, stem: 9963, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:36 +[UP] flip: 15, stem: 14948, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:36 +[UP] flip: 0, stem: 4981, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:21 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 9983, fault:3. flip_cnt: 3, stem_cnt: 85, fault_cnt:35 +[UP] flip: 0, stem: 14965, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:49 +[UP] flip: 12, stem: 14968, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:38 +[UP] flip: 33, stem: 4990, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 9985, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 34959, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:62 +[UP] flip: 5, stem: 4996, fault:9. flip_cnt: 2, stem_cnt: 94, fault_cnt:42 +[UP] flip: 9, stem: 14994, fault:20. flip_cnt: 3, stem_cnt: 85, fault_cnt:37 +[UP] flip: 12, stem: 9992, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 0, stem: 19983, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:53 +[UP] flip: 0, stem: 19988, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:52 +[UP] flip: 0, stem: 29987, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:52 +[UP] flip: 8, stem: 4996, fault:19. flip_cnt: 1, stem_cnt: 95, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 32, stem: 35023, fault:3. flip_cnt: 19, stem_cnt: 87, fault_cnt:37 +[UP] flip: 5, stem: 5005, fault:9. flip_cnt: 2, stem_cnt: 94, fault_cnt:52 +[UP] flip: 35, stem: 5006, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 5011, fault:3. flip_cnt: 7, stem_cnt: 91, fault_cnt:31 +[UP] flip: 27, stem: 3, fault:12. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 4, stem: 5010, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:56 +[UP] flip: 10, stem: 2, fault:24. flip_cnt: 2, stem_cnt: 94, fault_cnt:82 +[UP] flip: 35, stem: 3, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:77 +[UP] flip: 5, stem: 5015, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:85 +[UP] flip: 9, stem: 10027, fault:27. flip_cnt: 2, stem_cnt: 93, fault_cnt:110 +[UP] flip: 281, stem: 5014, fault:27. flip_cnt: 37, stem_cnt: 94, fault_cnt:76 +[UP] flip: 163, stem: 10031, fault:20. flip_cnt: 19, stem_cnt: 93, fault_cnt:102 +[UP] flip: 76, stem: 2, fault:19. flip_cnt: 9, stem_cnt: 94, fault_cnt:98 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 10038, fault:3. flip_cnt: 4, stem_cnt: 92, fault_cnt:21 +[UP] flip: 84, stem: 10040, fault:9. flip_cnt: 37, stem_cnt: 92, fault_cnt:35 +[UP] flip: 33, stem: 10043, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:45 +[UP] flip: 5, stem: 5023, fault:19. flip_cnt: 1, stem_cnt: 93, fault_cnt:93 +[UP] flip: 32, stem: 10044, fault:19. flip_cnt: 9, stem_cnt: 92, fault_cnt:97 +[UP] flip: 27, stem: 15070, fault:19. flip_cnt: 5, stem_cnt: 86, fault_cnt:95 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 25126, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:15 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 5029, fault:3. flip_cnt: 1, stem_cnt: 93, fault_cnt:46 +[UP] flip: 24, stem: 5029, fault:9. flip_cnt: 9, stem_cnt: 94, fault_cnt:46 +[UP] flip: 48, stem: 10059, fault:20. flip_cnt: 19, stem_cnt: 93, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 20127, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:19 +[UP] flip: 2, stem: 20131, fault:9. flip_cnt: 1, stem_cnt: 89, fault_cnt:71 +[UP] flip: 28, stem: 10064, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:55 +[UP] flip: 15, stem: 15103, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:49 +[UP] flip: 0, stem: 20139, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:42 +[UP] flip: 37, stem: 15111, fault:20. flip_cnt: 7, stem_cnt: 90, fault_cnt:35 +[UP] flip: 0, stem: 20143, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:41 +[UP] flip: 93, stem: 15111, fault:20. flip_cnt: 16, stem_cnt: 93, fault_cnt:31 +[UP] flip: 21, stem: 15109, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:32 +[UP] flip: 7, stem: 5041, fault:29. flip_cnt: 2, stem_cnt: 94, fault_cnt:47 +[UP] flip: 24, stem: 5031, fault:29. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 25, stem: 5031, fault:29. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 31, stem: 5031, fault:29. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 35, stem: 5031, fault:29. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 114, stem: 10065, fault:29. flip_cnt: 9, stem_cnt: 93, fault_cnt:46 +[UP] flip: 16, stem: 5031, fault:29. flip_cnt: 2, stem_cnt: 94, fault_cnt:89 +[UP] flip: 16, stem: 5030, fault:29. flip_cnt: 2, stem_cnt: 95, fault_cnt:84 +[UP] flip: 24, stem: 20148, fault:29. flip_cnt: 2, stem_cnt: 94, fault_cnt:85 +[UP] flip: 8, stem: 10078, fault:29. flip_cnt: 2, stem_cnt: 94, fault_cnt:86 +[UP] flip: 27, stem: 5031, fault:29. flip_cnt: 2, stem_cnt: 94, fault_cnt:86 +[UP] flip: 109, stem: 10064, fault:29. flip_cnt: 9, stem_cnt: 93, fault_cnt:81 +[UP] flip: 124, stem: 25217, fault:19. flip_cnt: 7, stem_cnt: 92, fault_cnt:94 +[UP] flip: 21, stem: 35287, fault:19. flip_cnt: 1, stem_cnt: 86, fault_cnt:88 +[UP] flip: 39, stem: 5035, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:120 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 15169, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:21 +[UP] flip: 27, stem: 1, fault:9. flip_cnt: 11, stem_cnt: 95, fault_cnt:14 +[UP] flip: 0, stem: 5068, fault:20. flip_cnt: 0, stem_cnt: 85, fault_cnt:27 +[UP] flip: 0, stem: 10117, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:27 +[UP] flip: 0, stem: 20237, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:24 +[UP] flip: 22, stem: 35417, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:11 +[UP] flip: 47, stem: 30360, fault:20. flip_cnt: 7, stem_cnt: 92, fault_cnt:35 +[UP] flip: 25, stem: 15190, fault:19. flip_cnt: 3, stem_cnt: 92, fault_cnt:26 +[UP] flip: 286, stem: 20247, fault:19. flip_cnt: 37, stem_cnt: 92, fault_cnt:33 +[UP] flip: 11, stem: 20247, fault:19. flip_cnt: 2, stem_cnt: 93, fault_cnt:43 +[UP] flip: 24, stem: 5064, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 25, stem: 5064, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 23, stem: 5064, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 34, stem: 5064, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 27, stem: 5064, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 33, stem: 5064, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 26, stem: 5064, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 24, stem: 5064, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 15, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:91 +[UP] flip: 37, stem: 5075, fault:39. flip_cnt: 2, stem_cnt: 95, fault_cnt:94 +[UP] flip: 33, stem: 2, fault:39. flip_cnt: 2, stem_cnt: 94, fault_cnt:91 +[UP] flip: 137, stem: 5067, fault:39. flip_cnt: 9, stem_cnt: 93, fault_cnt:88 +[UP] flip: 16, stem: 25305, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:88 +[UP] flip: 16, stem: 10130, fault:19. flip_cnt: 1, stem_cnt: 87, fault_cnt:91 +[UP] flip: 65, stem: 45685, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:77 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 15247, fault:3. flip_cnt: 3, stem_cnt: 92, fault_cnt:34 +[UP] flip: 0, stem: 10175, fault:9. flip_cnt: 0, stem_cnt: 85, fault_cnt:27 +[UP] flip: 8, stem: 5083, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 12, stem: 5083, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 16, stem: 5083, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 16, stem: 5083, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 23, stem: 5083, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 6, stem: 2, fault:23. flip_cnt: 1, stem_cnt: 94, fault_cnt:82 +[UP] flip: 120, stem: 5092, fault:20. flip_cnt: 15, stem_cnt: 93, fault_cnt:74 +[UP] flip: 15, stem: 5092, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:80 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 20374, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:63 +[UP] flip: 0, stem: 15281, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:72 +[UP] flip: 13, stem: 25484, fault:20. flip_cnt: 5, stem_cnt: 82, fault_cnt:51 +[UP] flip: 11, stem: 20379, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:50 +[UP] flip: 16, stem: 20378, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:45 +[UP] flip: 29, stem: 15284, fault:20. flip_cnt: 5, stem_cnt: 94, fault_cnt:49 +[UP] flip: 9, stem: 20382, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:46 +[UP] flip: 19, stem: 10198, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:64 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 20410, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:60 +[UP] flip: 31, stem: 20411, fault:9. flip_cnt: 11, stem_cnt: 92, fault_cnt:72 +[UP] flip: 0, stem: 10209, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:64 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:65 +[UP] flip: 0, stem: 5102, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:63 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 30649, fault:3. flip_cnt: 4, stem_cnt: 89, fault_cnt:38 +[UP] flip: 83, stem: 5111, fault:9. flip_cnt: 37, stem_cnt: 93, fault_cnt:28 +[UP] flip: 0, stem: 5111, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:22 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 25561, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:32 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:57 +[UP] flip: 0, stem: 5116, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:39 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 25581, fault:3. flip_cnt: 4, stem_cnt: 90, fault_cnt:20 +[UP] flip: 29, stem: 30701, fault:9. flip_cnt: 12, stem_cnt: 90, fault_cnt:50 +[UP] flip: 22, stem: 10235, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:38 +[UP] flip: 0, stem: 25588, fault:24. flip_cnt: 0, stem_cnt: 87, fault_cnt:38 +[UP] flip: 0, stem: 25588, fault:24. flip_cnt: 0, stem_cnt: 87, fault_cnt:38 +[UP] flip: 0, stem: 25588, fault:24. flip_cnt: 0, stem_cnt: 87, fault_cnt:38 +[UP] flip: 0, stem: 10239, fault:24. flip_cnt: 0, stem_cnt: 94, fault_cnt:38 +[UP] flip: 89, stem: 5119, fault:20. flip_cnt: 12, stem_cnt: 94, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 46, stem: 20500, fault:3. flip_cnt: 28, stem_cnt: 92, fault_cnt:68 +[UP] flip: 4, stem: 1, fault:3. flip_cnt: 2, stem_cnt: 95, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 30770, fault:3. flip_cnt: 9, stem_cnt: 88, fault_cnt:70 +[UP] flip: 23, stem: 10259, fault:9. flip_cnt: 8, stem_cnt: 93, fault_cnt:47 +[UP] flip: 13, stem: 20520, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:43 +[UP] flip: 0, stem: 15392, fault:24. flip_cnt: 0, stem_cnt: 93, fault_cnt:56 +[UP] flip: 42, stem: 5131, fault:20. flip_cnt: 8, stem_cnt: 94, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 5135, fault:3. flip_cnt: 11, stem_cnt: 94, fault_cnt:38 +[UP] flip: 32, stem: 2, fault:9. flip_cnt: 20, stem_cnt: 94, fault_cnt:51 +[UP] flip: 8, stem: 2, fault:23. flip_cnt: 3, stem_cnt: 94, fault_cnt:57 +[UP] flip: 40, stem: 10273, fault:23. flip_cnt: 9, stem_cnt: 92, fault_cnt:56 +[UP] flip: 2, stem: 15415, fault:20. flip_cnt: 1, stem_cnt: 89, fault_cnt:59 +[UP] flip: 54, stem: 15418, fault:26. flip_cnt: 9, stem_cnt: 91, fault_cnt:69 +[UP] flip: 11, stem: 20561, fault:26. flip_cnt: 2, stem_cnt: 91, fault_cnt:92 +[UP] flip: 23, stem: 1, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:79 +[UP] flip: 275, stem: 5140, fault:20. flip_cnt: 37, stem_cnt: 94, fault_cnt:77 +[UP] flip: 95, stem: 10288, fault:20. flip_cnt: 11, stem_cnt: 92, fault_cnt:107 +[UP] flip: 204, stem: 5147, fault:20. flip_cnt: 23, stem_cnt: 92, fault_cnt:101 +[UP] flip: 187, stem: 5147, fault:20. flip_cnt: 19, stem_cnt: 93, fault_cnt:102 +[UP] flip: 65, stem: 5143, fault:20. flip_cnt: 6, stem_cnt: 94, fault_cnt:74 +[UP] flip: 8, stem: 5142, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:76 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 20605, fault:3. flip_cnt: 3, stem_cnt: 83, fault_cnt:43 +[UP] flip: 16, stem: 20599, fault:9. flip_cnt: 7, stem_cnt: 92, fault_cnt:37 +[UP] flip: 9, stem: 20599, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:31 +[UP] flip: 7, stem: 15456, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:46 +[UP] flip: 31, stem: 10307, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:40 +[UP] flip: 0, stem: 5155, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:35 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 36099, fault:3. flip_cnt: 7, stem_cnt: 89, fault_cnt:15 +[UP] flip: 11, stem: 15480, fault:9. flip_cnt: 5, stem_cnt: 86, fault_cnt:43 +[UP] flip: 13, stem: 15476, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:13 +[UP] flip: 27, stem: 10314, fault:24. flip_cnt: 7, stem_cnt: 94, fault_cnt:39 +[UP] flip: 26, stem: 10314, fault:24. flip_cnt: 7, stem_cnt: 94, fault_cnt:39 +[UP] flip: 31, stem: 10314, fault:24. flip_cnt: 7, stem_cnt: 94, fault_cnt:39 +[UP] flip: 16, stem: 5157, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:59 +[UP] flip: 13, stem: 5157, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:59 +[UP] flip: 16, stem: 5157, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:59 +[UP] flip: 18, stem: 5157, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:59 +[UP] flip: 20, stem: 5157, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:59 +[UP] flip: 43, stem: 5157, fault:24. flip_cnt: 5, stem_cnt: 95, fault_cnt:63 +[UP] flip: 90, stem: 10317, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:58 +[UP] flip: 24, stem: 10319, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:48 +[UP] flip: 28, stem: 5158, fault:34. flip_cnt: 3, stem_cnt: 95, fault_cnt:66 +[UP] flip: 359, stem: 5161, fault:20. flip_cnt: 27, stem_cnt: 93, fault_cnt:51 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 72, stem: 15524, fault:3. flip_cnt: 37, stem_cnt: 91, fault_cnt:27 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 25881, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:18 +[UP] flip: 2, stem: 5179, fault:9. flip_cnt: 1, stem_cnt: 93, fault_cnt:33 +[UP] flip: 42, stem: 5176, fault:20. flip_cnt: 15, stem_cnt: 95, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 15542, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:46 +[UP] flip: 6, stem: 5188, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:51 +[UP] flip: 0, stem: 10365, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:45 +[UP] flip: 0, stem: 5182, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:32 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 36296, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:54 +[UP] flip: 0, stem: 15557, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:39 +[UP] flip: 0, stem: 15559, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:35 +[UP] flip: 0, stem: 20747, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:38 +[UP] flip: 15, stem: 1, fault:19. flip_cnt: 4, stem_cnt: 95, fault_cnt:45 +[UP] flip: 19, stem: 1, fault:19. flip_cnt: 4, stem_cnt: 95, fault_cnt:21 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 15577, fault:3. flip_cnt: 5, stem_cnt: 92, fault_cnt:39 +[UP] flip: 22, stem: 10387, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:37 +[UP] flip: 0, stem: 10389, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:30 +[UP] flip: 58, stem: 10389, fault:19. flip_cnt: 13, stem_cnt: 94, fault_cnt:34 +[UP] flip: 184, stem: 5193, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:25 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 31189, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:50 +[UP] flip: 33, stem: 25995, fault:10. flip_cnt: 12, stem_cnt: 91, fault_cnt:45 +[UP] flip: 25, stem: 15602, fault:19. flip_cnt: 7, stem_cnt: 91, fault_cnt:33 +[UP] flip: 136, stem: 15599, fault:19. flip_cnt: 37, stem_cnt: 93, fault_cnt:31 +[UP] flip: 29, stem: 10399, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:56 +[UP] flip: 0, stem: 36395, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:59 +[UP] flip: 0, stem: 36395, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:54 +[UP] flip: 0, stem: 36395, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:59 +[UP] flip: 81, stem: 15613, fault:19. flip_cnt: 10, stem_cnt: 93, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 15626, fault:3. flip_cnt: 2, stem_cnt: 91, fault_cnt:33 +[UP] flip: 23, stem: 5210, fault:9. flip_cnt: 9, stem_cnt: 94, fault_cnt:20 +[UP] flip: 5, stem: 2, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 5215, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:77 +[UP] flip: 11, stem: 5214, fault:9. flip_cnt: 4, stem_cnt: 94, fault_cnt:48 +[UP] flip: 12, stem: 10429, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:53 +[UP] flip: 13, stem: 5216, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:65 +[UP] flip: 53, stem: 15644, fault:20. flip_cnt: 10, stem_cnt: 93, fault_cnt:39 +[UP] flip: 194, stem: 5219, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:25 +[UP] flip: 5, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 20883, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:34 +[UP] flip: 29, stem: 2, fault:9. flip_cnt: 11, stem_cnt: 94, fault_cnt:32 +[UP] flip: 0, stem: 5222, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:45 +[UP] flip: 0, stem: 10445, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:45 +[UP] flip: 0, stem: 15667, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:45 +[UP] flip: 0, stem: 20892, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:45 +[UP] flip: 0, stem: 26116, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:45 +[UP] flip: 0, stem: 31343, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:43 +[UP] flip: 150, stem: 41790, fault:20. flip_cnt: 18, stem_cnt: 93, fault_cnt:34 +[UP] flip: 7, stem: 41800, fault:20. flip_cnt: 1, stem_cnt: 92, fault_cnt:24 +[UP] flip: 30, stem: 15692, fault:19. flip_cnt: 3, stem_cnt: 86, fault_cnt:42 +[UP] flip: 47, stem: 5233, fault:19. flip_cnt: 4, stem_cnt: 93, fault_cnt:41 +[UP] flip: 0, stem: 15695, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 20937, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:25 +[UP] flip: 25, stem: 20942, fault:9. flip_cnt: 9, stem_cnt: 90, fault_cnt:43 +[UP] flip: 0, stem: 10473, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:43 +[UP] flip: 0, stem: 5236, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 11, stem: 20958, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:45 +[UP] flip: 16, stem: 15719, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:55 +[UP] flip: 0, stem: 10483, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:33 +[UP] flip: 12, stem: 10481, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:36 +[UP] flip: 152, stem: 2, fault:20. flip_cnt: 37, stem_cnt: 94, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 26226, fault:3. flip_cnt: 1, stem_cnt: 90, fault_cnt:15 +[UP] flip: 0, stem: 20985, fault:9. flip_cnt: 0, stem_cnt: 91, fault_cnt:22 +[UP] flip: 105, stem: 15738, fault:20. flip_cnt: 37, stem_cnt: 92, fault_cnt:21 +[UP] flip: 30, stem: 10493, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:30 +[UP] flip: 42, stem: 5245, fault:19. flip_cnt: 10, stem_cnt: 95, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 31507, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:25 +[UP] flip: 6, stem: 10506, fault:9. flip_cnt: 2, stem_cnt: 92, fault_cnt:41 +[UP] flip: 15, stem: 10502, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:37 +[UP] flip: 38, stem: 5253, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:46 +[UP] flip: 121, stem: 4, fault:20. flip_cnt: 27, stem_cnt: 92, fault_cnt:71 +[UP] flip: 6, stem: 5257, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:66 +[UP] flip: 176, stem: 5254, fault:19. flip_cnt: 27, stem_cnt: 95, fault_cnt:57 +[UP] flip: 71, stem: 5253, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:56 +[UP] flip: 20, stem: 0, fault:19. flip_cnt: 3, stem_cnt: 96, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 15791, fault:3. flip_cnt: 0, stem_cnt: 85, fault_cnt:49 +[UP] flip: 18, stem: 15787, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:44 +[UP] flip: 0, stem: 10524, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:45 +[UP] flip: 34, stem: 1, fault:20. flip_cnt: 7, stem_cnt: 95, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 10533, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:41 +[UP] flip: 2, stem: 5268, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:38 +[UP] flip: 28, stem: 10534, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:43 +[UP] flip: 11, stem: 10543, fault:20. flip_cnt: 3, stem_cnt: 86, fault_cnt:37 +[UP] flip: 22, stem: 10542, fault:19. flip_cnt: 4, stem_cnt: 92, fault_cnt:30 +[UP] flip: 9, stem: 21083, fault:19. flip_cnt: 2, stem_cnt: 92, fault_cnt:32 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 26368, fault:3. flip_cnt: 9, stem_cnt: 88, fault_cnt:69 +[UP] flip: 6, stem: 10550, fault:9. flip_cnt: 2, stem_cnt: 92, fault_cnt:76 +[UP] flip: 82, stem: 10550, fault:24. flip_cnt: 28, stem_cnt: 93, fault_cnt:50 +[UP] flip: 13, stem: 10549, fault:24. flip_cnt: 3, stem_cnt: 94, fault_cnt:47 +[UP] flip: 11, stem: 5273, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 14, stem: 5273, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 17, stem: 5273, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 19, stem: 5273, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 19, stem: 5273, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 25, stem: 5273, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 32, stem: 5273, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:47 +[UP] flip: 101, stem: 5276, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:46 +[UP] flip: 11, stem: 5275, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:78 +[UP] flip: 29, stem: 10549, fault:34. flip_cnt: 2, stem_cnt: 94, fault_cnt:78 +[UP] flip: 26, stem: 5274, fault:34. flip_cnt: 2, stem_cnt: 94, fault_cnt:78 +[UP] flip: 28, stem: 10562, fault:34. flip_cnt: 2, stem_cnt: 93, fault_cnt:82 +[UP] flip: 8, stem: 5274, fault:34. flip_cnt: 2, stem_cnt: 94, fault_cnt:78 +[UP] flip: 36, stem: 5274, fault:34. flip_cnt: 2, stem_cnt: 94, fault_cnt:78 +[UP] flip: 34, stem: 5274, fault:34. flip_cnt: 2, stem_cnt: 94, fault_cnt:78 +[UP] flip: 115, stem: 10532, fault:34. flip_cnt: 9, stem_cnt: 93, fault_cnt:73 +[UP] flip: 18, stem: 15825, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:83 +[UP] flip: 18, stem: 21137, fault:39. flip_cnt: 1, stem_cnt: 86, fault_cnt:88 +[UP] flip: 695, stem: 5295, fault:39. flip_cnt: 37, stem_cnt: 94, fault_cnt:75 +[UP] flip: 6, stem: 5276, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:110 +[UP] flip: 382, stem: 1, fault:19. flip_cnt: 18, stem_cnt: 95, fault_cnt:108 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 15900, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:31 +[UP] flip: 16, stem: 15903, fault:9. flip_cnt: 9, stem_cnt: 90, fault_cnt:29 +[UP] flip: 5, stem: 26502, fault:20. flip_cnt: 2, stem_cnt: 91, fault_cnt:28 +[UP] flip: 53, stem: 5303, fault:19. flip_cnt: 11, stem_cnt: 94, fault_cnt:65 +[UP] flip: 5, stem: 5302, fault:19. flip_cnt: 1, stem_cnt: 95, fault_cnt:64 +[UP] flip: 163, stem: 5300, fault:19. flip_cnt: 27, stem_cnt: 95, fault_cnt:51 +[UP] flip: 45, stem: 5303, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:48 +[UP] flip: 19, stem: 10606, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 15, stem: 21235, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:83 +[UP] flip: 36, stem: 37164, fault:9. flip_cnt: 12, stem_cnt: 88, fault_cnt:39 +[UP] flip: 0, stem: 10621, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:55 +[UP] flip: 0, stem: 5310, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:56 +[UP] flip: 37, stem: 1, fault:20. flip_cnt: 7, stem_cnt: 95, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 21257, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:43 +[UP] flip: 3, stem: 5316, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:38 +[UP] flip: 0, stem: 21265, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:28 +[UP] flip: 0, stem: 10633, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:44 +[UP] flip: 17, stem: 0, fault:20. flip_cnt: 4, stem_cnt: 96, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 15961, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 26611, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:21 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 26621, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:51 +[UP] flip: 10, stem: 1, fault:9. flip_cnt: 4, stem_cnt: 95, fault_cnt:73 +[UP] flip: 7, stem: 5327, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:39 +[UP] flip: 171, stem: 15977, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 26648, fault:3. flip_cnt: 9, stem_cnt: 88, fault_cnt:29 +[UP] flip: 20, stem: 21319, fault:9. flip_cnt: 7, stem_cnt: 92, fault_cnt:48 +[UP] flip: 0, stem: 10668, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:33 +[UP] flip: 0, stem: 10665, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:40 +[UP] flip: 40, stem: 10664, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:37 +[UP] flip: 136, stem: 5335, fault:19. flip_cnt: 23, stem_cnt: 94, fault_cnt:48 +[UP] flip: 11, stem: 10665, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 21349, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:36 +[UP] flip: 9, stem: 9, fault:9. flip_cnt: 3, stem_cnt: 87, fault_cnt:40 +[UP] flip: 13, stem: 16016, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:24 +[UP] flip: 22, stem: 2, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:40 +[UP] flip: 176, stem: 5343, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:34 +[UP] flip: 0, stem: 5343, fault:26. flip_cnt: 0, stem_cnt: 94, fault_cnt:56 +[UP] flip: 29, stem: 10684, fault:26. flip_cnt: 5, stem_cnt: 94, fault_cnt:55 +[UP] flip: 19, stem: 5341, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:58 +[UP] flip: 21, stem: 5341, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:58 +[UP] flip: 25, stem: 5341, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:58 +[UP] flip: 26, stem: 5341, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:58 +[UP] flip: 11, stem: 10690, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:64 +[UP] flip: 339, stem: 16049, fault:19. flip_cnt: 29, stem_cnt: 91, fault_cnt:44 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 16054, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:39 +[UP] flip: 11, stem: 5354, fault:9. flip_cnt: 4, stem_cnt: 93, fault_cnt:27 +[UP] flip: 8, stem: 16060, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:22 +[UP] flip: 40, stem: 3, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:46 +[UP] flip: 3, stem: 2, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:86 +[UP] flip: 63, stem: 16066, fault:20. flip_cnt: 11, stem_cnt: 92, fault_cnt:79 +[UP] flip: 0, stem: 5358, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:101 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 26797, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:33 +[UP] flip: 43, stem: 10721, fault:9. flip_cnt: 19, stem_cnt: 93, fault_cnt:40 +[UP] flip: 7, stem: 5362, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:62 +[UP] flip: 9, stem: 5362, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:60 +[UP] flip: 5, stem: 5361, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 26834, fault:3. flip_cnt: 0, stem_cnt: 82, fault_cnt:24 +[UP] flip: 21, stem: 10731, fault:9. flip_cnt: 9, stem_cnt: 94, fault_cnt:66 +[UP] flip: 12, stem: 16099, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 21477, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:26 +[UP] flip: 6, stem: 5370, fault:9. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 5, stem: 10748, fault:20. flip_cnt: 3, stem_cnt: 86, fault_cnt:47 +[UP] flip: 19, stem: 10745, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:45 +[UP] flip: 37, stem: 16115, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:23 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 16127, fault:3. flip_cnt: 4, stem_cnt: 91, fault_cnt:35 +[UP] flip: 5, stem: 5383, fault:11. flip_cnt: 3, stem_cnt: 87, fault_cnt:45 +[UP] flip: 0, stem: 5378, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:52 +[UP] flip: 8, stem: 5378, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:52 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 16143, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:39 +[UP] flip: 6, stem: 10771, fault:10. flip_cnt: 3, stem_cnt: 85, fault_cnt:49 +[UP] flip: 4, stem: 16145, fault:19. flip_cnt: 2, stem_cnt: 92, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 5385, fault:3. flip_cnt: 4, stem_cnt: 94, fault_cnt:21 +[UP] flip: 17, stem: 3, fault:9. flip_cnt: 7, stem_cnt: 93, fault_cnt:17 +[UP] flip: 0, stem: 5387, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:27 +[UP] flip: 0, stem: 10772, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:27 +[UP] flip: 39, stem: 16161, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:36 +[UP] flip: 0, stem: 21548, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 10785, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:57 +[UP] flip: 21, stem: 26961, fault:9. flip_cnt: 7, stem_cnt: 90, fault_cnt:29 +[UP] flip: 21, stem: 10786, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:45 +[UP] flip: 10, stem: 32357, fault:20. flip_cnt: 3, stem_cnt: 86, fault_cnt:44 +[UP] flip: 0, stem: 21576, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:33 +[UP] flip: 53, stem: 37751, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:34 +[UP] flip: 61, stem: 10785, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 16198, fault:3. flip_cnt: 3, stem_cnt: 92, fault_cnt:31 +[UP] flip: 18, stem: 5403, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:40 +[UP] flip: 3, stem: 4, fault:11. flip_cnt: 1, stem_cnt: 92, fault_cnt:40 +[UP] flip: 105, stem: 16208, fault:20. flip_cnt: 37, stem_cnt: 91, fault_cnt:39 +[UP] flip: 2, stem: 10805, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 54058, fault:3. flip_cnt: 0, stem_cnt: 78, fault_cnt:17 +[UP] flip: 22, stem: 16219, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:44 +[UP] flip: 4, stem: 16218, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:106 +[UP] flip: 135, stem: 16227, fault:20. flip_cnt: 35, stem_cnt: 90, fault_cnt:72 +[UP] flip: 139, stem: 10815, fault:20. flip_cnt: 27, stem_cnt: 94, fault_cnt:64 +[UP] flip: 48, stem: 5409, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:52 +[UP] flip: 0, stem: 5408, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 19, stem: 21654, fault:3. flip_cnt: 11, stem_cnt: 90, fault_cnt:36 +[UP] flip: 20, stem: 5417, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:42 +[UP] flip: 3, stem: 21661, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:45 +[UP] flip: 32, stem: 16250, fault:20. flip_cnt: 9, stem_cnt: 88, fault_cnt:96 +[UP] flip: 17, stem: 10832, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:82 +[UP] flip: 41, stem: 0, fault:20. flip_cnt: 7, stem_cnt: 96, fault_cnt:88 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 3, stem: 21685, fault:3. flip_cnt: 2, stem_cnt: 87, fault_cnt:28 +[UP] flip: 44, stem: 27108, fault:10. flip_cnt: 20, stem_cnt: 88, fault_cnt:41 +[UP] flip: 0, stem: 5420, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 16274, fault:4. flip_cnt: 4, stem_cnt: 91, fault_cnt:52 +[UP] flip: 77, stem: 4, fault:8. flip_cnt: 27, stem_cnt: 92, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:17. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 22, stem: 10854, fault:3. flip_cnt: 12, stem_cnt: 94, fault_cnt:53 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 16290, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:53 +[UP] flip: 0, stem: 21719, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:31 +[UP] flip: 0, stem: 10868, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:36 +[UP] flip: 0, stem: 16297, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:46 +[UP] flip: 47, stem: 1, fault:19. flip_cnt: 11, stem_cnt: 95, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 10871, fault:3. flip_cnt: 1, stem_cnt: 93, fault_cnt:45 +[UP] flip: 52, stem: 5438, fault:10. flip_cnt: 20, stem_cnt: 93, fault_cnt:38 +[UP] flip: 30, stem: 2, fault:18. flip_cnt: 9, stem_cnt: 94, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 16318, fault:3. flip_cnt: 2, stem_cnt: 92, fault_cnt:28 +[UP] flip: 6, stem: 1, fault:10. flip_cnt: 3, stem_cnt: 95, fault_cnt:43 +[UP] flip: 30, stem: 1, fault:19. flip_cnt: 11, stem_cnt: 95, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 9, stem: 27215, fault:3. flip_cnt: 5, stem_cnt: 91, fault_cnt:45 +[UP] flip: 20, stem: 10887, fault:9. flip_cnt: 9, stem_cnt: 93, fault_cnt:57 +[UP] flip: 11, stem: 16336, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:42 +[UP] flip: 15, stem: 16339, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:43 +[UP] flip: 19, stem: 10893, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:45 +[UP] flip: 23, stem: 0, fault:19. flip_cnt: 4, stem_cnt: 96, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 32701, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:41 +[UP] flip: 5, stem: 2, fault:3. flip_cnt: 3, stem_cnt: 94, fault_cnt:44 +[UP] flip: 22, stem: 5455, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:43 +[UP] flip: 3, stem: 5454, fault:23. flip_cnt: 1, stem_cnt: 94, fault_cnt:52 +[UP] flip: 155, stem: 10910, fault:23. flip_cnt: 37, stem_cnt: 92, fault_cnt:52 +[UP] flip: 11, stem: 10911, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:41 +[UP] flip: 69, stem: 5457, fault:19. flip_cnt: 11, stem_cnt: 93, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 27291, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:31 +[UP] flip: 0, stem: 5460, fault:9. flip_cnt: 0, stem_cnt: 94, fault_cnt:44 +[UP] flip: 15, stem: 10920, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:40 +[UP] flip: 5, stem: 27296, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:37 +[UP] flip: 0, stem: 10925, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:43 +[UP] flip: 0, stem: 5462, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:27 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 32791, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:30 +[UP] flip: 7, stem: 5468, fault:11. flip_cnt: 4, stem_cnt: 93, fault_cnt:40 +[UP] flip: 0, stem: 5467, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:43 +[UP] flip: 29, stem: 2, fault:21. flip_cnt: 7, stem_cnt: 94, fault_cnt:36 +[UP] flip: 36, stem: 5472, fault:21. flip_cnt: 9, stem_cnt: 92, fault_cnt:30 +[UP] flip: 11, stem: 0, fault:18. flip_cnt: 2, stem_cnt: 96, fault_cnt:54 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 16417, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:31 +[UP] flip: 6, stem: 5472, fault:9. flip_cnt: 2, stem_cnt: 95, fault_cnt:42 +[UP] flip: 9, stem: 5474, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 10, stem: 10949, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:37 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 16443, fault:3. flip_cnt: 7, stem_cnt: 84, fault_cnt:67 +[UP] flip: 14, stem: 5486, fault:4. flip_cnt: 7, stem_cnt: 87, fault_cnt:58 +[UP] flip: 18, stem: 43837, fault:10. flip_cnt: 7, stem_cnt: 89, fault_cnt:56 +[UP] flip: 105, stem: 5479, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:19 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 16450, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:27 +[UP] flip: 10, stem: 32905, fault:9. flip_cnt: 4, stem_cnt: 89, fault_cnt:40 +[UP] flip: 27, stem: 10970, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:40 +[UP] flip: 10, stem: 16453, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:41 +[UP] flip: 25, stem: 16454, fault:20. flip_cnt: 5, stem_cnt: 94, fault_cnt:40 +[UP] flip: 34, stem: 16452, fault:20. flip_cnt: 5, stem_cnt: 94, fault_cnt:37 +[UP] flip: 36, stem: 21940, fault:20. flip_cnt: 5, stem_cnt: 94, fault_cnt:39 +[UP] flip: 49, stem: 16460, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:38 +[UP] flip: 0, stem: 43887, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:38 +[UP] flip: 11, stem: 38427, fault:20. flip_cnt: 2, stem_cnt: 90, fault_cnt:40 +[UP] flip: 14, stem: 27453, fault:20. flip_cnt: 2, stem_cnt: 92, fault_cnt:37 +[UP] flip: 32, stem: 27458, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:47 +[UP] flip: 57, stem: 10978, fault:20. flip_cnt: 5, stem_cnt: 94, fault_cnt:46 +[UP] flip: 13, stem: 10992, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:50 +[UP] flip: 82, stem: 16490, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:49 +[UP] flip: 71, stem: 10981, fault:20. flip_cnt: 5, stem_cnt: 94, fault_cnt:54 +[UP] flip: 136, stem: 5498, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 17, stem: 16492, fault:19. flip_cnt: 1, stem_cnt: 93, fault_cnt:64 +[UP] flip: 22, stem: 10954, fault:38. flip_cnt: 2, stem_cnt: 94, fault_cnt:98 +[UP] flip: 15, stem: 5479, fault:38. flip_cnt: 2, stem_cnt: 94, fault_cnt:96 +[UP] flip: 4, stem: 5479, fault:38. flip_cnt: 2, stem_cnt: 94, fault_cnt:98 +[UP] flip: 134, stem: 16450, fault:38. flip_cnt: 9, stem_cnt: 93, fault_cnt:93 +[UP] flip: 16, stem: 5478, fault:38. flip_cnt: 2, stem_cnt: 94, fault_cnt:97 +[UP] flip: 148, stem: 10945, fault:38. flip_cnt: 9, stem_cnt: 93, fault_cnt:93 +[UP] flip: 18, stem: 43899, fault:38. flip_cnt: 1, stem_cnt: 86, fault_cnt:99 +[UP] flip: 232, stem: 5499, fault:19. flip_cnt: 11, stem_cnt: 94, fault_cnt:88 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 21, stem: 11021, fault:3. flip_cnt: 11, stem_cnt: 93, fault_cnt:62 +[UP] flip: 3, stem: 5513, fault:9. flip_cnt: 1, stem_cnt: 93, fault_cnt:45 +[UP] flip: 7, stem: 16537, fault:20. flip_cnt: 2, stem_cnt: 92, fault_cnt:61 +[UP] flip: 5, stem: 5514, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:83 +[UP] flip: 9, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:88 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 22065, fault:3. flip_cnt: 7, stem_cnt: 91, fault_cnt:28 +[UP] flip: 3, stem: 16553, fault:9. flip_cnt: 1, stem_cnt: 91, fault_cnt:11 +[UP] flip: 31, stem: 1, fault:20. flip_cnt: 9, stem_cnt: 95, fault_cnt:17 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 33121, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:27 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 27610, fault:3. flip_cnt: 7, stem_cnt: 91, fault_cnt:39 +[UP] flip: 3, stem: 1, fault:9. flip_cnt: 1, stem_cnt: 95, fault_cnt:54 +[UP] flip: 0, stem: 5524, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:56 +[UP] flip: 89, stem: 11050, fault:20. flip_cnt: 19, stem_cnt: 93, fault_cnt:48 +[UP] flip: 51, stem: 2, fault:19. flip_cnt: 9, stem_cnt: 94, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 5529, fault:3. flip_cnt: 3, stem_cnt: 94, fault_cnt:30 +[UP] flip: 15, stem: 11062, fault:9. flip_cnt: 7, stem_cnt: 90, fault_cnt:19 +[UP] flip: 18, stem: 5529, fault:23. flip_cnt: 5, stem_cnt: 95, fault_cnt:49 +[UP] flip: 10, stem: 5529, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 16, stem: 5529, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 17, stem: 5529, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 16, stem: 5529, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 14, stem: 5529, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:45 +[UP] flip: 16, stem: 5537, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:56 +[UP] flip: 2, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:80 +[UP] flip: 21, stem: 2, fault:31. flip_cnt: 2, stem_cnt: 94, fault_cnt:80 +[UP] flip: 94, stem: 3, fault:31. flip_cnt: 9, stem_cnt: 93, fault_cnt:75 +[UP] flip: 7, stem: 3, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:83 +[UP] flip: 7, stem: 11091, fault:20. flip_cnt: 1, stem_cnt: 85, fault_cnt:82 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 27716, fault:3. flip_cnt: 1, stem_cnt: 90, fault_cnt:14 +[UP] flip: 0, stem: 11089, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:37 +[UP] flip: 0, stem: 5544, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:27 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 1, fault:3. flip_cnt: 0, stem_cnt: 95, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 22197, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:35 +[UP] flip: 0, stem: 5559, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:25 +[UP] flip: 0, stem: 33307, fault:20. flip_cnt: 0, stem_cnt: 89, fault_cnt:15 +[UP] flip: 0, stem: 27761, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:25 +[UP] flip: 0, stem: 5551, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:21 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 55551, fault:3. flip_cnt: 0, stem_cnt: 85, fault_cnt:15 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 27786, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:30 +[UP] flip: 0, stem: 5565, fault:10. flip_cnt: 0, stem_cnt: 87, fault_cnt:33 +[UP] flip: 0, stem: 5560, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:33 +[UP] flip: 0, stem: 5559, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:33 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 16687, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:44 +[UP] flip: 17, stem: 11126, fault:10. flip_cnt: 7, stem_cnt: 93, fault_cnt:33 +[UP] flip: 12, stem: 5563, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 14, stem: 5566, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:33 +[UP] flip: 36, stem: 11131, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:39 +[UP] flip: 42, stem: 11131, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:38 +[UP] flip: 0, stem: 5569, fault:26. flip_cnt: 0, stem_cnt: 94, fault_cnt:55 +[UP] flip: 17, stem: 5566, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 23, stem: 5566, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 32, stem: 5566, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 22, stem: 5566, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 49, stem: 5566, fault:26. flip_cnt: 5, stem_cnt: 95, fault_cnt:56 +[UP] flip: 27, stem: 5566, fault:26. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 110, stem: 5568, fault:26. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 14, stem: 16706, fault:19. flip_cnt: 1, stem_cnt: 92, fault_cnt:62 +[UP] flip: 0, stem: 5578, fault:35. flip_cnt: 0, stem_cnt: 94, fault_cnt:90 +[UP] flip: 5, stem: 5564, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:84 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 39061, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:14 +[UP] flip: 19, stem: 1, fault:9. flip_cnt: 7, stem_cnt: 95, fault_cnt:31 +[UP] flip: 0, stem: 5584, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:26 +[UP] flip: 28, stem: 11169, fault:20. flip_cnt: 7, stem_cnt: 91, fault_cnt:25 +[UP] flip: 13, stem: 11168, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 16759, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:51 +[UP] flip: 0, stem: 11176, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:43 +[UP] flip: 9, stem: 16765, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:24 +[UP] flip: 0, stem: 11177, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 11, stem: 16773, fault:3. flip_cnt: 7, stem_cnt: 93, fault_cnt:32 +[UP] flip: 2, stem: 1, fault:9. flip_cnt: 1, stem_cnt: 95, fault_cnt:32 +[UP] flip: 30, stem: 5594, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:28 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 22382, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:39 +[UP] flip: 18, stem: 27980, fault:9. flip_cnt: 7, stem_cnt: 90, fault_cnt:23 +[UP] flip: 0, stem: 16789, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:39 +[UP] flip: 27, stem: 5596, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:39 +[UP] flip: 14, stem: 27987, fault:20. flip_cnt: 3, stem_cnt: 86, fault_cnt:38 +[UP] flip: 35, stem: 16796, fault:20. flip_cnt: 7, stem_cnt: 92, fault_cnt:23 +[UP] flip: 52, stem: 16805, fault:19. flip_cnt: 8, stem_cnt: 90, fault_cnt:11 +[UP] flip: 66, stem: 16803, fault:28. flip_cnt: 10, stem_cnt: 94, fault_cnt:41 +[UP] flip: 19, stem: 5595, fault:28. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 33, stem: 5595, fault:28. flip_cnt: 5, stem_cnt: 95, fault_cnt:55 +[UP] flip: 26, stem: 5595, fault:28. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 41, stem: 5595, fault:28. flip_cnt: 5, stem_cnt: 95, fault_cnt:56 +[UP] flip: 48, stem: 5595, fault:28. flip_cnt: 5, stem_cnt: 95, fault_cnt:56 +[UP] flip: 29, stem: 5595, fault:28. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 120, stem: 11192, fault:28. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 17, stem: 16805, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:66 +[UP] flip: 49, stem: 5596, fault:37. flip_cnt: 4, stem_cnt: 95, fault_cnt:69 +[UP] flip: 52, stem: 5601, fault:37. flip_cnt: 4, stem_cnt: 95, fault_cnt:61 +[UP] flip: 58, stem: 5601, fault:37. flip_cnt: 4, stem_cnt: 95, fault_cnt:61 +[UP] flip: 5, stem: 1, fault:37. flip_cnt: 1, stem_cnt: 95, fault_cnt:95 +[UP] flip: 409, stem: 5602, fault:20. flip_cnt: 27, stem_cnt: 93, fault_cnt:81 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 5618, fault:3. flip_cnt: 7, stem_cnt: 94, fault_cnt:39 +[UP] flip: 19, stem: 11236, fault:9. flip_cnt: 7, stem_cnt: 94, fault_cnt:33 +[UP] flip: 0, stem: 5620, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:35 +[UP] flip: 144, stem: 5622, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:33 +[UP] flip: 55, stem: 11241, fault:20. flip_cnt: 13, stem_cnt: 94, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 22500, fault:3. flip_cnt: 3, stem_cnt: 84, fault_cnt:35 +[UP] flip: 35, stem: 11250, fault:9. flip_cnt: 15, stem_cnt: 92, fault_cnt:41 +[UP] flip: 10, stem: 5624, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 147, stem: 2, fault:20. flip_cnt: 37, stem_cnt: 94, fault_cnt:48 +[UP] flip: 3, stem: 1, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:65 +[UP] flip: 155, stem: 3, fault:20. flip_cnt: 27, stem_cnt: 93, fault_cnt:52 +[UP] flip: 19, stem: 5630, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:51 +[UP] flip: 20, stem: 0, fault:19. flip_cnt: 3, stem_cnt: 96, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 33, stem: 22529, fault:3. flip_cnt: 19, stem_cnt: 91, fault_cnt:66 +[UP] flip: 39, stem: 16901, fault:9. flip_cnt: 15, stem_cnt: 91, fault_cnt:31 +[UP] flip: 35, stem: 11269, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:31 +[UP] flip: 4, stem: 11268, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:30 +[UP] flip: 38, stem: 28169, fault:19. flip_cnt: 7, stem_cnt: 93, fault_cnt:25 +[UP] flip: 53, stem: 11267, fault:26. flip_cnt: 9, stem_cnt: 94, fault_cnt:37 +[UP] flip: 0, stem: 22541, fault:26. flip_cnt: 0, stem_cnt: 86, fault_cnt:37 +[UP] flip: 0, stem: 11272, fault:26. flip_cnt: 0, stem_cnt: 94, fault_cnt:37 +[UP] flip: 35, stem: 5632, fault:26. flip_cnt: 5, stem_cnt: 95, fault_cnt:51 +[UP] flip: 38, stem: 5634, fault:26. flip_cnt: 4, stem_cnt: 94, fault_cnt:43 +[UP] flip: 62, stem: 5634, fault:26. flip_cnt: 7, stem_cnt: 94, fault_cnt:42 +[UP] flip: 85, stem: 5634, fault:26. flip_cnt: 9, stem_cnt: 93, fault_cnt:53 +[UP] flip: 14, stem: 11276, fault:26. flip_cnt: 1, stem_cnt: 94, fault_cnt:67 +[UP] flip: 319, stem: 5636, fault:20. flip_cnt: 27, stem_cnt: 93, fault_cnt:71 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 16944, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:40 +[UP] flip: 3, stem: 11297, fault:9. flip_cnt: 1, stem_cnt: 93, fault_cnt:42 +[UP] flip: 38, stem: 16948, fault:20. flip_cnt: 11, stem_cnt: 92, fault_cnt:73 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:90 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 16959, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:60 +[UP] flip: 14, stem: 16959, fault:9. flip_cnt: 5, stem_cnt: 93, fault_cnt:38 +[UP] flip: 0, stem: 11309, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:34 +[UP] flip: 0, stem: 5655, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:63 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 16980, fault:3. flip_cnt: 0, stem_cnt: 84, fault_cnt:54 +[UP] flip: 8, stem: 5658, fault:9. flip_cnt: 3, stem_cnt: 95, fault_cnt:78 +[UP] flip: 0, stem: 5661, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:81 +[UP] flip: 0, stem: 5661, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:86 +[UP] flip: 15, stem: 5660, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:85 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 45305, fault:3. flip_cnt: 0, stem_cnt: 87, fault_cnt:31 +[UP] flip: 0, stem: 5666, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:35 +[UP] flip: 0, stem: 11329, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:31 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:27 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:27 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 39685, fault:3. flip_cnt: 0, stem_cnt: 87, fault_cnt:33 +[UP] flip: 27, stem: 11342, fault:9. flip_cnt: 15, stem_cnt: 92, fault_cnt:19 +[UP] flip: 24, stem: 17011, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:35 +[UP] flip: 11, stem: 5670, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 12, stem: 5670, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 26, stem: 5670, fault:20. flip_cnt: 5, stem_cnt: 95, fault_cnt:52 +[UP] flip: 25, stem: 5670, fault:20. flip_cnt: 5, stem_cnt: 95, fault_cnt:51 +[UP] flip: 20, stem: 5670, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 17, stem: 5670, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 25, stem: 5670, fault:20. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 89, stem: 11339, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:47 +[UP] flip: 9, stem: 17030, fault:31. flip_cnt: 1, stem_cnt: 93, fault_cnt:56 +[UP] flip: 23, stem: 5682, fault:31. flip_cnt: 2, stem_cnt: 94, fault_cnt:98 +[UP] flip: 87, stem: 3, fault:31. flip_cnt: 9, stem_cnt: 93, fault_cnt:88 +[UP] flip: 11, stem: 22717, fault:20. flip_cnt: 1, stem_cnt: 88, fault_cnt:90 +[UP] flip: 48, stem: 22722, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:75 +[UP] flip: 26, stem: 5681, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:78 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 28436, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:62 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 22762, fault:3. flip_cnt: 1, stem_cnt: 86, fault_cnt:80 +[UP] flip: 14, stem: 22761, fault:10. flip_cnt: 9, stem_cnt: 90, fault_cnt:90 +[UP] flip: 87, stem: 17072, fault:19. flip_cnt: 37, stem_cnt: 92, fault_cnt:23 +[UP] flip: 28, stem: 22769, fault:19. flip_cnt: 7, stem_cnt: 91, fault_cnt:33 +[UP] flip: 0, stem: 11385, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:24 +[UP] flip: 36, stem: 3, fault:19. flip_cnt: 7, stem_cnt: 93, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 37, stem: 17090, fault:3. flip_cnt: 19, stem_cnt: 91, fault_cnt:38 +[UP] flip: 13, stem: 5696, fault:10. flip_cnt: 5, stem_cnt: 95, fault_cnt:46 +[UP] flip: 9, stem: 5699, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:36 +[UP] flip: 37, stem: 3, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:49 +[UP] flip: 6, stem: 11401, fault:23. flip_cnt: 1, stem_cnt: 93, fault_cnt:90 +[UP] flip: 12, stem: 11401, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:89 +[UP] flip: 14, stem: 2, fault:23. flip_cnt: 2, stem_cnt: 94, fault_cnt:86 +[UP] flip: 53, stem: 3, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:81 +[UP] flip: 8, stem: 17107, fault:23. flip_cnt: 1, stem_cnt: 86, fault_cnt:90 +[UP] flip: 9, stem: 22809, fault:19. flip_cnt: 1, stem_cnt: 90, fault_cnt:105 +[UP] flip: 223, stem: 17116, fault:19. flip_cnt: 22, stem_cnt: 93, fault_cnt:80 +[UP] flip: 11, stem: 22813, fault:19. flip_cnt: 1, stem_cnt: 86, fault_cnt:84 +[UP] flip: 49, stem: 17104, fault:19. flip_cnt: 4, stem_cnt: 93, fault_cnt:65 +[UP] flip: 146, stem: 11417, fault:19. flip_cnt: 11, stem_cnt: 93, fault_cnt:100 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 20, stem: 17135, fault:3. flip_cnt: 11, stem_cnt: 91, fault_cnt:40 +[UP] flip: 5, stem: 5714, fault:10. flip_cnt: 2, stem_cnt: 93, fault_cnt:53 +[UP] flip: 12, stem: 5714, fault:22. flip_cnt: 3, stem_cnt: 94, fault_cnt:49 +[UP] flip: 41, stem: 3, fault:22. flip_cnt: 9, stem_cnt: 93, fault_cnt:44 +[UP] flip: 6, stem: 2, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:82 +[UP] flip: 1, stem: 2, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:82 +[UP] flip: 79, stem: 1, fault:19. flip_cnt: 13, stem_cnt: 95, fault_cnt:80 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 22877, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:32 +[UP] flip: 0, stem: 11441, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:48 +[UP] flip: 0, stem: 5722, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:35 +[UP] flip: 0, stem: 5723, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:38 +[UP] flip: 0, stem: 11444, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:38 +[UP] flip: 0, stem: 17167, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:38 +[UP] flip: 0, stem: 22892, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 22909, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:46 +[UP] flip: 0, stem: 11457, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:37 +[UP] flip: 8, stem: 5730, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 1, stem: 5732, fault:3. flip_cnt: 1, stem_cnt: 94, fault_cnt:39 +[UP] flip: 20, stem: 5733, fault:10. flip_cnt: 7, stem_cnt: 94, fault_cnt:45 +[UP] flip: 64, stem: 5736, fault:19. flip_cnt: 20, stem_cnt: 92, fault_cnt:33 +[UP] flip: 92, stem: 4, fault:19. flip_cnt: 27, stem_cnt: 92, fault_cnt:35 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11473, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:23 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 40167, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:54 +[UP] flip: 0, stem: 5748, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:50 +[UP] flip: 13, stem: 11481, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:58 +[UP] flip: 16, stem: 11481, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:35 +[UP] flip: 0, stem: 17221, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:57 +[UP] flip: 0, stem: 22965, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:57 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 23, stem: 22982, fault:3. flip_cnt: 12, stem_cnt: 90, fault_cnt:12 +[UP] flip: 19, stem: 5748, fault:10. flip_cnt: 7, stem_cnt: 93, fault_cnt:30 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 22994, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:59 +[UP] flip: 22, stem: 11497, fault:9. flip_cnt: 8, stem_cnt: 94, fault_cnt:51 +[UP] flip: 0, stem: 5751, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:51 +[UP] flip: 0, stem: 11501, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:49 +[UP] flip: 0, stem: 17253, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:47 +[UP] flip: 0, stem: 28757, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:47 +[UP] flip: 0, stem: 28756, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:46 +[UP] flip: 6, stem: 34511, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:43 +[UP] flip: 0, stem: 40265, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:43 +[UP] flip: 0, stem: 46022, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:45 +[UP] flip: 0, stem: 51778, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:43 +[UP] flip: 29, stem: 51779, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:40 +[UP] flip: 20, stem: 5761, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:41 +[UP] flip: 31, stem: 11510, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:34 +[UP] flip: 91, stem: 17260, fault:19. flip_cnt: 9, stem_cnt: 92, fault_cnt:30 +[UP] flip: 11, stem: 11511, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:78 +[UP] flip: 121, stem: 1, fault:19. flip_cnt: 13, stem_cnt: 95, fault_cnt:80 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 34597, fault:3. flip_cnt: 1, stem_cnt: 89, fault_cnt:60 +[UP] flip: 22, stem: 5768, fault:10. flip_cnt: 9, stem_cnt: 93, fault_cnt:98 +[UP] flip: 6, stem: 17305, fault:19. flip_cnt: 2, stem_cnt: 92, fault_cnt:69 +[UP] flip: 15, stem: 17306, fault:19. flip_cnt: 4, stem_cnt: 93, fault_cnt:77 +[UP] flip: 51, stem: 3, fault:19. flip_cnt: 11, stem_cnt: 93, fault_cnt:73 +[UP] flip: 70, stem: 2, fault:19. flip_cnt: 13, stem_cnt: 94, fault_cnt:80 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 17322, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:24 +[UP] flip: 3, stem: 5775, fault:9. flip_cnt: 1, stem_cnt: 94, fault_cnt:39 +[UP] flip: 70, stem: 5777, fault:20. flip_cnt: 27, stem_cnt: 93, fault_cnt:42 +[UP] flip: 0, stem: 5777, fault:24. flip_cnt: 0, stem_cnt: 94, fault_cnt:50 +[UP] flip: 34, stem: 5774, fault:24. flip_cnt: 7, stem_cnt: 94, fault_cnt:39 +[UP] flip: 38, stem: 5774, fault:24. flip_cnt: 7, stem_cnt: 94, fault_cnt:39 +[UP] flip: 65, stem: 2, fault:24. flip_cnt: 9, stem_cnt: 94, fault_cnt:33 +[UP] flip: 6, stem: 11551, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:41 +[UP] flip: 28, stem: 5773, fault:29. flip_cnt: 4, stem_cnt: 95, fault_cnt:50 +[UP] flip: 4, stem: 11550, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:80 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 28921, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:32 +[UP] flip: 3, stem: 23142, fault:10. flip_cnt: 1, stem_cnt: 90, fault_cnt:71 +[UP] flip: 9, stem: 5787, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:42 +[UP] flip: 15, stem: 5784, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 14, stem: 5784, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 14, stem: 5784, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 16, stem: 5784, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 17, stem: 5784, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 27, stem: 5784, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 29, stem: 5784, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 30, stem: 5784, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:44 +[UP] flip: 97, stem: 11571, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:43 +[UP] flip: 162, stem: 5798, fault:19. flip_cnt: 15, stem_cnt: 93, fault_cnt:83 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 23195, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:38 +[UP] flip: 0, stem: 17404, fault:9. flip_cnt: 0, stem_cnt: 85, fault_cnt:26 +[UP] flip: 0, stem: 11601, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:24 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 23209, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:38 +[UP] flip: 9, stem: 5804, fault:9. flip_cnt: 3, stem_cnt: 94, fault_cnt:48 +[UP] flip: 12, stem: 17418, fault:20. flip_cnt: 3, stem_cnt: 85, fault_cnt:43 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 17424, fault:3. flip_cnt: 1, stem_cnt: 90, fault_cnt:43 +[UP] flip: 20, stem: 17425, fault:10. flip_cnt: 9, stem_cnt: 91, fault_cnt:50 +[UP] flip: 0, stem: 5815, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:58 +[UP] flip: 0, stem: 34861, fault:19. flip_cnt: 0, stem_cnt: 89, fault_cnt:56 +[UP] flip: 0, stem: 40669, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:58 +[UP] flip: 0, stem: 40669, fault:19. flip_cnt: 0, stem_cnt: 87, fault_cnt:58 +[UP] flip: 25, stem: 11623, fault:19. flip_cnt: 5, stem_cnt: 94, fault_cnt:53 +[UP] flip: 89, stem: 5816, fault:19. flip_cnt: 15, stem_cnt: 93, fault_cnt:40 +[UP] flip: 73, stem: 5818, fault:28. flip_cnt: 9, stem_cnt: 92, fault_cnt:50 +[UP] flip: 7, stem: 5817, fault:28. flip_cnt: 1, stem_cnt: 94, fault_cnt:85 +[UP] flip: 58, stem: 2, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:102 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 34915, fault:3. flip_cnt: 0, stem_cnt: 89, fault_cnt:35 +[UP] flip: 20, stem: 11640, fault:9. flip_cnt: 9, stem_cnt: 93, fault_cnt:39 +[UP] flip: 44, stem: 17462, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:28 +[UP] flip: 30, stem: 11639, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:44 +[UP] flip: 17, stem: 11645, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:40 +[UP] flip: 0, stem: 17473, fault:19. flip_cnt: 0, stem_cnt: 92, fault_cnt:40 +[UP] flip: 31, stem: 5825, fault:19. flip_cnt: 4, stem_cnt: 95, fault_cnt:34 +[UP] flip: 121, stem: 4, fault:19. flip_cnt: 19, stem_cnt: 92, fault_cnt:15 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 34971, fault:3. flip_cnt: 3, stem_cnt: 87, fault_cnt:28 +[UP] flip: 19, stem: 1, fault:10. flip_cnt: 11, stem_cnt: 95, fault_cnt:17 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 11664, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:43 +[UP] flip: 5, stem: 5833, fault:9. flip_cnt: 2, stem_cnt: 94, fault_cnt:48 +[UP] flip: 66, stem: 5834, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:49 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 29176, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:14 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 23350, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:33 +[UP] flip: 6, stem: 11675, fault:9. flip_cnt: 2, stem_cnt: 94, fault_cnt:31 +[UP] flip: 4, stem: 5840, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 35047, fault:3. flip_cnt: 4, stem_cnt: 89, fault_cnt:17 +[UP] flip: 8, stem: 5844, fault:9. flip_cnt: 4, stem_cnt: 93, fault_cnt:48 +[UP] flip: 20, stem: 17526, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:87 +[UP] flip: 0, stem: 23378, fault:20. flip_cnt: 0, stem_cnt: 85, fault_cnt:93 +[UP] flip: 13, stem: 11686, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:67 +[UP] flip: 13, stem: 5847, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:77 +[UP] flip: 15, stem: 1, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:88 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 23397, fault:3. flip_cnt: 4, stem_cnt: 91, fault_cnt:30 +[UP] flip: 6, stem: 11701, fault:9. flip_cnt: 2, stem_cnt: 93, fault_cnt:41 +[UP] flip: 8, stem: 17552, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:43 +[UP] flip: 62, stem: 1, fault:20. flip_cnt: 16, stem_cnt: 95, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11709, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:60 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:75 +[UP] flip: 0, stem: 5857, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:69 +[UP] flip: 7, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:76 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 23437, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:46 +[UP] flip: 9, stem: 1, fault:10. flip_cnt: 3, stem_cnt: 95, fault_cnt:56 +[UP] flip: 33, stem: 3, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:55 +[UP] flip: 5, stem: 5862, fault:19. flip_cnt: 1, stem_cnt: 95, fault_cnt:107 +[UP] flip: 37, stem: 2, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:101 +[UP] flip: 7, stem: 1, fault:19. flip_cnt: 1, stem_cnt: 95, fault_cnt:119 +[UP] flip: 177, stem: 5861, fault:19. flip_cnt: 27, stem_cnt: 95, fault_cnt:106 +[UP] flip: 57, stem: 11725, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:93 +[UP] flip: 9, stem: 11730, fault:19. flip_cnt: 1, stem_cnt: 94, fault_cnt:69 +[UP] flip: 126, stem: 1, fault:19. flip_cnt: 13, stem_cnt: 95, fault_cnt:75 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 5, stem: 35221, fault:3. flip_cnt: 3, stem_cnt: 89, fault_cnt:38 +[UP] flip: 29, stem: 5872, fault:9. flip_cnt: 10, stem_cnt: 94, fault_cnt:30 +[UP] flip: 0, stem: 5873, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:51 +[UP] flip: 8, stem: 11748, fault:24. flip_cnt: 2, stem_cnt: 92, fault_cnt:57 +[UP] flip: 12, stem: 11748, fault:24. flip_cnt: 3, stem_cnt: 94, fault_cnt:59 +[UP] flip: 23, stem: 5872, fault:24. flip_cnt: 4, stem_cnt: 94, fault_cnt:37 +[UP] flip: 53, stem: 5879, fault:24. flip_cnt: 9, stem_cnt: 92, fault_cnt:34 +[UP] flip: 14, stem: 5873, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:50 +[UP] flip: 29, stem: 5876, fault:29. flip_cnt: 4, stem_cnt: 95, fault_cnt:55 +[UP] flip: 110, stem: 5873, fault:20. flip_cnt: 12, stem_cnt: 94, fault_cnt:55 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 23524, fault:3. flip_cnt: 3, stem_cnt: 92, fault_cnt:28 +[UP] flip: 0, stem: 17647, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:43 +[UP] flip: 18, stem: 23530, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:42 +[UP] flip: 0, stem: 23532, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:42 +[UP] flip: 15, stem: 5886, fault:19. flip_cnt: 3, stem_cnt: 94, fault_cnt:35 +[UP] flip: 0, stem: 11770, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:42 +[UP] flip: 0, stem: 11772, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:45 +[UP] flip: 19, stem: 0, fault:19. flip_cnt: 3, stem_cnt: 96, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 35349, fault:3. flip_cnt: 0, stem_cnt: 81, fault_cnt:19 +[UP] flip: 21, stem: 17674, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:64 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 17680, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:16 +[UP] flip: 14, stem: 5895, fault:9. flip_cnt: 6, stem_cnt: 94, fault_cnt:64 +[UP] flip: 32, stem: 17683, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:29 +[UP] flip: 35, stem: 11792, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:24 +[UP] flip: 5, stem: 2, fault:20. flip_cnt: 1, stem_cnt: 94, fault_cnt:31 +[UP] flip: 0, stem: 11793, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 17701, fault:3. flip_cnt: 2, stem_cnt: 92, fault_cnt:56 +[UP] flip: 50, stem: 17704, fault:9. flip_cnt: 19, stem_cnt: 92, fault_cnt:49 +[UP] flip: 10, stem: 11803, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 29521, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:34 +[UP] flip: 18, stem: 17714, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:37 +[UP] flip: 20, stem: 5907, fault:23. flip_cnt: 7, stem_cnt: 94, fault_cnt:46 +[UP] flip: 14, stem: 5906, fault:23. flip_cnt: 5, stem_cnt: 95, fault_cnt:46 +[UP] flip: 175, stem: 5910, fault:23. flip_cnt: 37, stem_cnt: 93, fault_cnt:36 +[UP] flip: 50, stem: 3, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:48 +[UP] flip: 8, stem: 1, fault:23. flip_cnt: 1, stem_cnt: 95, fault_cnt:94 +[UP] flip: 141, stem: 2, fault:20. flip_cnt: 19, stem_cnt: 94, fault_cnt:83 +[UP] flip: 73, stem: 5914, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:76 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11830, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:65 +[UP] flip: 6, stem: 11833, fault:9. flip_cnt: 2, stem_cnt: 91, fault_cnt:56 +[UP] flip: 34, stem: 17749, fault:20. flip_cnt: 11, stem_cnt: 92, fault_cnt:28 +[UP] flip: 13, stem: 11831, fault:24. flip_cnt: 3, stem_cnt: 94, fault_cnt:41 +[UP] flip: 11, stem: 5914, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 15, stem: 5914, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 12, stem: 5914, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 20, stem: 5914, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 20, stem: 5914, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 27, stem: 5914, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 18, stem: 5914, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 95, stem: 11831, fault:24. flip_cnt: 9, stem_cnt: 93, fault_cnt:45 +[UP] flip: 10, stem: 11833, fault:24. flip_cnt: 1, stem_cnt: 93, fault_cnt:87 +[UP] flip: 4, stem: 23676, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:81 +[UP] flip: 0, stem: 11857, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:87 +[UP] flip: 26, stem: 2, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:81 +[UP] flip: 105, stem: 3, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:76 +[UP] flip: 18, stem: 11854, fault:20. flip_cnt: 1, stem_cnt: 86, fault_cnt:87 +[UP] flip: 61, stem: 17779, fault:20. flip_cnt: 4, stem_cnt: 93, fault_cnt:75 +[UP] flip: 18, stem: 17760, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:113 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 8, stem: 29677, fault:3. flip_cnt: 4, stem_cnt: 89, fault_cnt:23 +[UP] flip: 8, stem: 11873, fault:9. flip_cnt: 3, stem_cnt: 93, fault_cnt:22 +[UP] flip: 27, stem: 5937, fault:20. flip_cnt: 9, stem_cnt: 93, fault_cnt:48 +[UP] flip: 30, stem: 2, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:86 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 5944, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:55 +[UP] flip: 12, stem: 1, fault:10. flip_cnt: 4, stem_cnt: 95, fault_cnt:26 +[UP] flip: 123, stem: 2, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:19 +[UP] flip: 0, stem: 2, fault:19. flip_cnt: 0, stem_cnt: 94, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 1, stem: 41623, fault:3. flip_cnt: 1, stem_cnt: 88, fault_cnt:21 +[UP] flip: 4, stem: 17840, fault:10. flip_cnt: 2, stem_cnt: 93, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 16, stem: 1, fault:3. flip_cnt: 11, stem_cnt: 95, fault_cnt:20 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 29756, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:42 +[UP] flip: 24, stem: 5953, fault:9. flip_cnt: 9, stem_cnt: 93, fault_cnt:40 +[UP] flip: 2, stem: 17857, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:32 +[UP] flip: 0, stem: 5955, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:49 +[UP] flip: 180, stem: 5957, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:36 +[UP] flip: 51, stem: 11909, fault:26. flip_cnt: 9, stem_cnt: 92, fault_cnt:57 +[UP] flip: 6, stem: 17863, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:67 +[UP] flip: 85, stem: 17875, fault:19. flip_cnt: 13, stem_cnt: 92, fault_cnt:54 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:68 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 11923, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:31 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 63, stem: 23853, fault:3. flip_cnt: 37, stem_cnt: 91, fault_cnt:33 +[UP] flip: 37, stem: 1, fault:10. flip_cnt: 15, stem_cnt: 95, fault_cnt:49 +[UP] flip: 7, stem: 2, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:48 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 11937, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:44 +[UP] flip: 0, stem: 11945, fault:9. flip_cnt: 0, stem_cnt: 85, fault_cnt:45 +[UP] flip: 0, stem: 23877, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:34 +[UP] flip: 18, stem: 23881, fault:20. flip_cnt: 4, stem_cnt: 91, fault_cnt:20 +[UP] flip: 0, stem: 5970, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:38 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 17920, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:39 +[UP] flip: 0, stem: 11955, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:42 +[UP] flip: 0, stem: 41824, fault:20. flip_cnt: 0, stem_cnt: 89, fault_cnt:40 +[UP] flip: 6, stem: 5976, fault:20. flip_cnt: 2, stem_cnt: 92, fault_cnt:31 +[UP] flip: 0, stem: 5975, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:37 +[UP] flip: 25, stem: 1, fault:20. flip_cnt: 4, stem_cnt: 95, fault_cnt:20 +[UP] flip: 204, stem: 2, fault:20. flip_cnt: 37, stem_cnt: 94, fault_cnt:19 +[UP] flip: 0, stem: 2, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:34 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 17949, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:47 +[UP] flip: 5, stem: 11969, fault:9. flip_cnt: 2, stem_cnt: 91, fault_cnt:40 +[UP] flip: 67, stem: 11967, fault:20. flip_cnt: 23, stem_cnt: 94, fault_cnt:41 +[UP] flip: 31, stem: 23941, fault:24. flip_cnt: 7, stem_cnt: 91, fault_cnt:28 +[UP] flip: 13, stem: 5985, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 10, stem: 5987, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:37 +[UP] flip: 52, stem: 5985, fault:20. flip_cnt: 8, stem_cnt: 94, fault_cnt:43 +[UP] flip: 110, stem: 2, fault:19. flip_cnt: 15, stem_cnt: 94, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 41939, fault:3. flip_cnt: 4, stem_cnt: 87, fault_cnt:32 +[UP] flip: 0, stem: 17977, fault:11. flip_cnt: 0, stem_cnt: 92, fault_cnt:36 +[UP] flip: 7, stem: 11992, fault:19. flip_cnt: 3, stem_cnt: 86, fault_cnt:45 +[UP] flip: 27, stem: 11990, fault:19. flip_cnt: 7, stem_cnt: 92, fault_cnt:47 +[UP] flip: 11, stem: 11988, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:38 +[UP] flip: 76, stem: 5994, fault:19. flip_cnt: 12, stem_cnt: 94, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 10, stem: 35997, fault:3. flip_cnt: 5, stem_cnt: 81, fault_cnt:63 +[UP] flip: 7, stem: 11999, fault:9. flip_cnt: 3, stem_cnt: 93, fault_cnt:53 +[UP] flip: 34, stem: 12001, fault:20. flip_cnt: 10, stem_cnt: 93, fault_cnt:25 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:57 +[UP] flip: 15, stem: 0, fault:20. flip_cnt: 3, stem_cnt: 96, fault_cnt:60 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 20, stem: 12009, fault:3. flip_cnt: 11, stem_cnt: 93, fault_cnt:39 +[UP] flip: 0, stem: 6014, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:50 +[UP] flip: 0, stem: 18019, fault:20. flip_cnt: 0, stem_cnt: 92, fault_cnt:46 +[UP] flip: 0, stem: 6006, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:56 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 24037, fault:3. flip_cnt: 4, stem_cnt: 91, fault_cnt:51 +[UP] flip: 3, stem: 18031, fault:9. flip_cnt: 1, stem_cnt: 92, fault_cnt:49 +[UP] flip: 0, stem: 12021, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:52 +[UP] flip: 0, stem: 6011, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:60 +[UP] flip: 56, stem: 1, fault:20. flip_cnt: 10, stem_cnt: 95, fault_cnt:43 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 42108, fault:3. flip_cnt: 9, stem_cnt: 86, fault_cnt:69 +[UP] flip: 9, stem: 24063, fault:10. flip_cnt: 3, stem_cnt: 92, fault_cnt:37 +[UP] flip: 14, stem: 12035, fault:19. flip_cnt: 4, stem_cnt: 93, fault_cnt:47 +[UP] flip: 10, stem: 6020, fault:19. flip_cnt: 2, stem_cnt: 93, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 36122, fault:3. flip_cnt: 1, stem_cnt: 88, fault_cnt:41 +[UP] flip: 2, stem: 18065, fault:10. flip_cnt: 1, stem_cnt: 90, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 30116, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:33 +[UP] flip: 0, stem: 12050, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:23 +[UP] flip: 0, stem: 12056, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:20 +[UP] flip: 8, stem: 12049, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:37 +[UP] flip: 19, stem: 138576, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:42 +[UP] flip: 34, stem: 168697, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:41 +[UP] flip: 40, stem: 78297, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:43 +[UP] flip: 16, stem: 24092, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 39, stem: 18062, fault:27. flip_cnt: 5, stem_cnt: 95, fault_cnt:58 +[UP] flip: 21, stem: 12031, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 20, stem: 5999, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 48, stem: 5999, fault:27. flip_cnt: 5, stem_cnt: 95, fault_cnt:59 +[UP] flip: 56, stem: 5999, fault:27. flip_cnt: 5, stem_cnt: 95, fault_cnt:58 +[UP] flip: 34, stem: 5999, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 24, stem: 5999, fault:27. flip_cnt: 3, stem_cnt: 95, fault_cnt:55 +[UP] flip: 114, stem: 12053, fault:27. flip_cnt: 9, stem_cnt: 93, fault_cnt:54 +[UP] flip: 16, stem: 18093, fault:27. flip_cnt: 1, stem_cnt: 94, fault_cnt:75 +[UP] flip: 30, stem: 6024, fault:27. flip_cnt: 2, stem_cnt: 94, fault_cnt:92 +[UP] flip: 29, stem: 11935, fault:27. flip_cnt: 2, stem_cnt: 94, fault_cnt:61 +[UP] flip: 123, stem: 78268, fault:20. flip_cnt: 7, stem_cnt: 94, fault_cnt:85 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 30221, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:52 +[UP] flip: 12, stem: 24181, fault:9. flip_cnt: 4, stem_cnt: 91, fault_cnt:66 +[UP] flip: 19, stem: 18137, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:63 +[UP] flip: 48, stem: 12092, fault:20. flip_cnt: 11, stem_cnt: 93, fault_cnt:53 +[UP] flip: 0, stem: 36277, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:58 +[UP] flip: 17, stem: 6045, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:62 +[UP] flip: 19, stem: 1, fault:19. flip_cnt: 3, stem_cnt: 95, fault_cnt:52 +[UP] flip: 59, stem: 3, fault:19. flip_cnt: 9, stem_cnt: 93, fault_cnt:51 +[UP] flip: 9, stem: 6054, fault:19. flip_cnt: 1, stem_cnt: 93, fault_cnt:65 +[UP] flip: 236, stem: 12103, fault:19. flip_cnt: 27, stem_cnt: 92, fault_cnt:78 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 24221, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:55 +[UP] flip: 0, stem: 1, fault:9. flip_cnt: 0, stem_cnt: 95, fault_cnt:58 +[UP] flip: 0, stem: 6057, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:49 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 18, stem: 30296, fault:3. flip_cnt: 10, stem_cnt: 90, fault_cnt:34 +[UP] flip: 0, stem: 12121, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:42 +[UP] flip: 10, stem: 18184, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:36 +[UP] flip: 4, stem: 6061, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:49 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 48513, fault:3. flip_cnt: 0, stem_cnt: 87, fault_cnt:50 +[UP] flip: 8, stem: 24260, fault:9. flip_cnt: 3, stem_cnt: 92, fault_cnt:40 +[UP] flip: 11, stem: 6066, fault:23. flip_cnt: 4, stem_cnt: 95, fault_cnt:59 +[UP] flip: 14, stem: 6064, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 13, stem: 6064, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 16, stem: 6064, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 20, stem: 6064, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:50 +[UP] flip: 21, stem: 6064, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 26, stem: 6064, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 23, stem: 6064, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 35, stem: 6064, fault:23. flip_cnt: 3, stem_cnt: 95, fault_cnt:46 +[UP] flip: 92, stem: 6067, fault:23. flip_cnt: 9, stem_cnt: 93, fault_cnt:45 +[UP] flip: 13, stem: 2, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:79 +[UP] flip: 27, stem: 12143, fault:34. flip_cnt: 2, stem_cnt: 94, fault_cnt:84 +[UP] flip: 29, stem: 6065, fault:34. flip_cnt: 2, stem_cnt: 94, fault_cnt:81 +[UP] flip: 21, stem: 6065, fault:34. flip_cnt: 2, stem_cnt: 94, fault_cnt:81 +[UP] flip: 30, stem: 6065, fault:34. flip_cnt: 2, stem_cnt: 94, fault_cnt:79 +[UP] flip: 91, stem: 12130, fault:34. flip_cnt: 9, stem_cnt: 93, fault_cnt:76 +[UP] flip: 17, stem: 24290, fault:20. flip_cnt: 1, stem_cnt: 91, fault_cnt:84 +[UP] flip: 125, stem: 24312, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:79 +[UP] flip: 26, stem: 6067, fault:19. flip_cnt: 2, stem_cnt: 95, fault_cnt:113 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 12175, fault:3. flip_cnt: 9, stem_cnt: 91, fault_cnt:59 +[UP] flip: 9, stem: 1, fault:9. flip_cnt: 3, stem_cnt: 95, fault_cnt:49 +[UP] flip: 0, stem: 6089, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:57 +[UP] flip: 32, stem: 12178, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:36 +[UP] flip: 6, stem: 0, fault:19. flip_cnt: 1, stem_cnt: 96, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 24369, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:23 +[UP] flip: 102, stem: 6093, fault:10. flip_cnt: 37, stem_cnt: 94, fault_cnt:23 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 24380, fault:3. flip_cnt: 7, stem_cnt: 92, fault_cnt:35 +[UP] flip: 8, stem: 12199, fault:9. flip_cnt: 3, stem_cnt: 86, fault_cnt:40 +[UP] flip: 0, stem: 12195, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:24 +[UP] flip: 0, stem: 6097, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:24 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 18308, fault:3. flip_cnt: 0, stem_cnt: 85, fault_cnt:14 +[UP] flip: 20, stem: 30504, fault:9. flip_cnt: 7, stem_cnt: 91, fault_cnt:37 +[UP] flip: 4, stem: 18304, fault:20. flip_cnt: 1, stem_cnt: 93, fault_cnt:51 +[UP] flip: 12, stem: 24408, fault:19. flip_cnt: 3, stem_cnt: 87, fault_cnt:52 +[UP] flip: 14, stem: 18309, fault:19. flip_cnt: 3, stem_cnt: 93, fault_cnt:53 +[UP] flip: 71, stem: 24421, fault:19. flip_cnt: 11, stem_cnt: 91, fault_cnt:29 +[UP] flip: 59, stem: 12215, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:40 +[UP] flip: 9, stem: 6100, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:91 +[UP] flip: 15, stem: 6109, fault:28. flip_cnt: 2, stem_cnt: 94, fault_cnt:97 +[UP] flip: 17, stem: 6098, fault:28. flip_cnt: 2, stem_cnt: 94, fault_cnt:92 +[UP] flip: 9, stem: 6097, fault:28. flip_cnt: 2, stem_cnt: 95, fault_cnt:87 +[UP] flip: 21, stem: 6098, fault:28. flip_cnt: 2, stem_cnt: 94, fault_cnt:92 +[UP] flip: 100, stem: 18295, fault:28. flip_cnt: 9, stem_cnt: 93, fault_cnt:87 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 24457, fault:3. flip_cnt: 3, stem_cnt: 91, fault_cnt:44 +[UP] flip: 21, stem: 12231, fault:9. flip_cnt: 9, stem_cnt: 92, fault_cnt:46 +[UP] flip: 0, stem: 12233, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:41 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 14, stem: 12240, fault:3. flip_cnt: 8, stem_cnt: 90, fault_cnt:23 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 18361, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:59 +[UP] flip: 7, stem: 12251, fault:9. flip_cnt: 3, stem_cnt: 85, fault_cnt:48 +[UP] flip: 9, stem: 12245, fault:20. flip_cnt: 3, stem_cnt: 93, fault_cnt:41 +[UP] flip: 7, stem: 12245, fault:19. flip_cnt: 2, stem_cnt: 94, fault_cnt:46 +[UP] flip: 51, stem: 6125, fault:19. flip_cnt: 10, stem_cnt: 94, fault_cnt:28 +[UP] flip: 17, stem: 0, fault:19. flip_cnt: 3, stem_cnt: 96, fault_cnt:46 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 24509, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:42 +[UP] flip: 5, stem: 2, fault:10. flip_cnt: 2, stem_cnt: 94, fault_cnt:37 +[UP] flip: 34, stem: 2, fault:19. flip_cnt: 11, stem_cnt: 94, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 17, stem: 24526, fault:3. flip_cnt: 11, stem_cnt: 90, fault_cnt:29 +[UP] flip: 0, stem: 12265, fault:9. flip_cnt: 0, stem_cnt: 93, fault_cnt:31 +[UP] flip: 115, stem: 2, fault:20. flip_cnt: 37, stem_cnt: 94, fault_cnt:43 +[UP] flip: 8, stem: 1, fault:20. flip_cnt: 2, stem_cnt: 95, fault_cnt:61 +[UP] flip: 55, stem: 2, fault:20. flip_cnt: 11, stem_cnt: 94, fault_cnt:53 +[UP] flip: 0, stem: 6137, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:60 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 33, stem: 30697, fault:3. flip_cnt: 17, stem_cnt: 89, fault_cnt:23 +[UP] flip: 0, stem: 24559, fault:9. flip_cnt: 0, stem_cnt: 92, fault_cnt:42 +[UP] flip: 26, stem: 12280, fault:19. flip_cnt: 7, stem_cnt: 94, fault_cnt:42 +[UP] flip: 0, stem: 6142, fault:21. flip_cnt: 0, stem_cnt: 95, fault_cnt:51 +[UP] flip: 14, stem: 1, fault:24. flip_cnt: 3, stem_cnt: 95, fault_cnt:48 +[UP] flip: 47, stem: 12281, fault:24. flip_cnt: 7, stem_cnt: 94, fault_cnt:36 +[UP] flip: 79, stem: 2, fault:19. flip_cnt: 11, stem_cnt: 94, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 30736, fault:4. flip_cnt: 6, stem_cnt: 90, fault_cnt:44 +[UP] flip: 0, stem: 12305, fault:9. flip_cnt: 0, stem_cnt: 85, fault_cnt:41 +[UP] flip: 29, stem: 18445, fault:17. flip_cnt: 9, stem_cnt: 92, fault_cnt:39 +[UP] flip: 5, stem: 3, fault:18. flip_cnt: 1, stem_cnt: 93, fault_cnt:76 +[UP] flip: 7, stem: 2, fault:20. flip_cnt: 2, stem_cnt: 94, fault_cnt:87 +[UP] flip: 70, stem: 6153, fault:20. flip_cnt: 13, stem_cnt: 94, fault_cnt:74 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:86 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 24623, fault:3. flip_cnt: 9, stem_cnt: 89, fault_cnt:44 +[UP] flip: 71, stem: 24624, fault:9. flip_cnt: 27, stem_cnt: 91, fault_cnt:35 +[UP] flip: 13, stem: 24630, fault:20. flip_cnt: 4, stem_cnt: 90, fault_cnt:19 +[UP] flip: 129, stem: 24628, fault:20. flip_cnt: 37, stem_cnt: 92, fault_cnt:32 +[UP] flip: 10, stem: 24632, fault:25. flip_cnt: 2, stem_cnt: 93, fault_cnt:43 +[UP] flip: 5, stem: 36951, fault:25. flip_cnt: 1, stem_cnt: 93, fault_cnt:62 +[UP] flip: 2, stem: 6162, fault:25. flip_cnt: 2, stem_cnt: 94, fault_cnt:51 +[UP] flip: 17, stem: 6159, fault:25. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 25, stem: 6159, fault:25. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 26, stem: 6159, fault:25. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 24, stem: 6159, fault:25. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 20, stem: 6159, fault:25. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 29, stem: 6159, fault:25. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 36, stem: 6159, fault:25. flip_cnt: 3, stem_cnt: 95, fault_cnt:51 +[UP] flip: 66, stem: 6159, fault:25. flip_cnt: 5, stem_cnt: 95, fault_cnt:54 +[UP] flip: 122, stem: 12321, fault:25. flip_cnt: 9, stem_cnt: 93, fault_cnt:50 +[UP] flip: 15, stem: 6157, fault:20. flip_cnt: 1, stem_cnt: 95, fault_cnt:79 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 18520, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:38 +[UP] flip: 9, stem: 30869, fault:9. flip_cnt: 3, stem_cnt: 91, fault_cnt:38 +[UP] flip: 23, stem: 24698, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:53 +[UP] flip: 21, stem: 1, fault:19. flip_cnt: 5, stem_cnt: 95, fault_cnt:37 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 24713, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:65 +[UP] flip: 30, stem: 37076, fault:9. flip_cnt: 10, stem_cnt: 88, fault_cnt:27 +[UP] flip: 22, stem: 24720, fault:20. flip_cnt: 9, stem_cnt: 91, fault_cnt:16 +[UP] flip: 7, stem: 30899, fault:20. flip_cnt: 2, stem_cnt: 92, fault_cnt:23 +[UP] flip: 0, stem: 43259, fault:20. flip_cnt: 0, stem_cnt: 86, fault_cnt:33 +[UP] flip: 0, stem: 18545, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:34 +[UP] flip: 0, stem: 6183, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:47 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 12373, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:40 +[UP] flip: 25, stem: 6186, fault:9. flip_cnt: 9, stem_cnt: 95, fault_cnt:20 +[UP] flip: 0, stem: 6190, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:40 +[UP] flip: 0, stem: 12377, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:42 +[UP] flip: 0, stem: 18566, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:42 +[UP] flip: 0, stem: 24755, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:42 +[UP] flip: 43, stem: 30948, fault:20. flip_cnt: 7, stem_cnt: 93, fault_cnt:51 +[UP] flip: 49, stem: 49526, fault:20. flip_cnt: 7, stem_cnt: 91, fault_cnt:42 +[UP] flip: 140, stem: 37139, fault:20. flip_cnt: 15, stem_cnt: 94, fault_cnt:43 +[UP] flip: 184, stem: 1, fault:19. flip_cnt: 19, stem_cnt: 95, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 4, stem: 30986, fault:3. flip_cnt: 2, stem_cnt: 90, fault_cnt:19 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 6, stem: 43394, fault:3. flip_cnt: 3, stem_cnt: 88, fault_cnt:16 +[UP] flip: 21, stem: 18601, fault:9. flip_cnt: 9, stem_cnt: 91, fault_cnt:37 +[UP] flip: 6, stem: 18601, fault:20. flip_cnt: 2, stem_cnt: 93, fault_cnt:67 +[UP] flip: 121, stem: 18602, fault:20. flip_cnt: 27, stem_cnt: 94, fault_cnt:57 +[UP] flip: 33, stem: 24805, fault:20. flip_cnt: 9, stem_cnt: 92, fault_cnt:54 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 2, stem: 43436, fault:3. flip_cnt: 2, stem_cnt: 88, fault_cnt:80 +[UP] flip: 3, stem: 12415, fault:9. flip_cnt: 1, stem_cnt: 91, fault_cnt:17 +[UP] flip: 16, stem: 0, fault:20. flip_cnt: 5, stem_cnt: 96, fault_cnt:54 +[UP] flip: 12, stem: 12413, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:45 +[UP] flip: 0, stem: 12417, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:48 +[UP] flip: 12, stem: 18622, fault:20. flip_cnt: 3, stem_cnt: 94, fault_cnt:45 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 22, stem: 12426, fault:3. flip_cnt: 11, stem_cnt: 92, fault_cnt:43 +[UP] flip: 8, stem: 18648, fault:9. flip_cnt: 3, stem_cnt: 84, fault_cnt:46 +[UP] flip: 0, stem: 24857, fault:20. flip_cnt: 0, stem_cnt: 91, fault_cnt:44 +[UP] flip: 14, stem: 31074, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:46 +[UP] flip: 17, stem: 31074, fault:20. flip_cnt: 3, stem_cnt: 87, fault_cnt:46 +[UP] flip: 0, stem: 12431, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:34 +[UP] flip: 147, stem: 3, fault:20. flip_cnt: 27, stem_cnt: 93, fault_cnt:48 +[UP] flip: 172, stem: 6220, fault:20. flip_cnt: 27, stem_cnt: 93, fault_cnt:42 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 12, stem: 18666, fault:3. flip_cnt: 9, stem_cnt: 90, fault_cnt:24 +[UP] flip: 15, stem: 12447, fault:10. flip_cnt: 9, stem_cnt: 91, fault_cnt:59 +[UP] flip: 4, stem: 12444, fault:22. flip_cnt: 1, stem_cnt: 94, fault_cnt:78 +[UP] flip: 48, stem: 2, fault:19. flip_cnt: 11, stem_cnt: 94, fault_cnt:83 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 13, stem: 12454, fault:3. flip_cnt: 9, stem_cnt: 92, fault_cnt:32 +[UP] flip: 3, stem: 6229, fault:9. flip_cnt: 1, stem_cnt: 93, fault_cnt:28 +[UP] flip: 0, stem: 6229, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:27 +[UP] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 43618, fault:3. flip_cnt: 0, stem_cnt: 88, fault_cnt:27 +[UP] flip: 5, stem: 6234, fault:9. flip_cnt: 2, stem_cnt: 92, fault_cnt:37 +[UP] flip: 14, stem: 18700, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:46 +[UP] flip: 0, stem: 1, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:57 +[UP] flip: 0, stem: 6235, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:57 +[UP] flip: 63, stem: 1, fault:19. flip_cnt: 10, stem_cnt: 95, fault_cnt:40 +[UP] flip: 246, stem: 2, fault:19. flip_cnt: 37, stem_cnt: 94, fault_cnt:28 +[UP] flip: 7, stem: 1, fault:19. flip_cnt: 1, stem_cnt: 95, fault_cnt:40 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 24961, fault:3. flip_cnt: 0, stem_cnt: 91, fault_cnt:27 +[UP] flip: 0, stem: 1, fault:10. flip_cnt: 0, stem_cnt: 95, fault_cnt:50 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 31216, fault:3. flip_cnt: 0, stem_cnt: 90, fault_cnt:57 +[UP] flip: 8, stem: 12487, fault:10. flip_cnt: 3, stem_cnt: 94, fault_cnt:33 +[UP] flip: 25, stem: 12490, fault:19. flip_cnt: 9, stem_cnt: 92, fault_cnt:41 +[UP] flip: 9, stem: 6250, fault:19. flip_cnt: 3, stem_cnt: 88, fault_cnt:47 +[UP] flip: 0, stem: 12495, fault:19. flip_cnt: 0, stem_cnt: 93, fault_cnt:49 +[UP] flip: 0, stem: 6247, fault:19. flip_cnt: 0, stem_cnt: 95, fault_cnt:43 +[UP] flip: 28, stem: 1, fault:19. flip_cnt: 4, stem_cnt: 95, fault_cnt:26 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 12503, fault:3. flip_cnt: 0, stem_cnt: 93, fault_cnt:39 +[UP] flip: 19, stem: 1, fault:9. flip_cnt: 7, stem_cnt: 95, fault_cnt:24 +[UP] flip: 0, stem: 6255, fault:20. flip_cnt: 0, stem_cnt: 93, fault_cnt:50 +[UP] flip: 0, stem: 6255, fault:20. flip_cnt: 0, stem_cnt: 94, fault_cnt:56 +[UP] flip: 0, stem: 1, fault:20. flip_cnt: 0, stem_cnt: 95, fault_cnt:60 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:20. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 0, stem: 18772, fault:3. flip_cnt: 0, stem_cnt: 92, fault_cnt:44 +[UP] flip: 0, stem: 6267, fault:9. flip_cnt: 0, stem_cnt: 86, fault_cnt:38 +[UP] flip: 9, stem: 25035, fault:20. flip_cnt: 3, stem_cnt: 92, fault_cnt:35 +[UP] flip: 143, stem: 12520, fault:20. flip_cnt: 37, stem_cnt: 93, fault_cnt:25 +FIND SOLUTION! +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 0.9923 pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +local search! +[UP] flip: 7, stem: 6264, fault:3. flip_cnt: 4, stem_cnt: 93, fault_cnt:30 +[UP] flip: 87, stem: 12528, fault:9. flip_cnt: 37, stem_cnt: 92, fault_cnt:29 +[UP] flip: 0, stem: 18798, fault:20. flip_cnt: 0, stem_cnt: 85, fault_cnt:46 +[UP] flip: 15, stem: 18796, fault:20. flip_cnt: 4, stem_cnt: 92, fault_cnt:56 +[UP] flip: 19, stem: 12529, fault:20. flip_cnt: 4, stem_cnt: 94, fault_cnt:30 +[UP] flip: 0, stem: 6268, fault:2 \ No newline at end of file