# generated by verilog2bench.py https://gitea.yuhangq.com/YuhangQ/any2bench INPUT(NET_1) INPUT(NET_2) INPUT(NET_3) INPUT(NET_4) INPUT(NET_5) OUTPUT(NET_12) OUTPUT(NET_23) OUTPUT(NET_27) OUTPUT(NET_28) OUTPUT(NET_6) new_n11_ = NOT ( NET_3 ) new_n12_ = NOT ( NET_4 ) NET_12 = AND ( new_n12_, new_n11_, NET_2 ) new_n14_ = NOR ( new_n11_, NET_2 ) new_n15_ = NAND ( new_n14_, new_n12_ ) new_n16_ = NOR ( NET_3, NET_1 ) new_n17_ = NOR ( new_n16_, NET_2 ) new_n18_ = OR ( new_n17_, new_n12_ ) NET_23 = NAND ( new_n18_, new_n15_ ) new_n20_ = NOR ( new_n11_, NET_1 ) new_n21_ = OR ( new_n20_, NET_4 ) new_n22_ = NAND ( new_n21_, NET_2 ) new_n23_ = NOT ( NET_1 ) new_n24_ = NOR ( new_n14_, NET_4 ) new_n25_ = OR ( new_n24_, new_n23_ ) new_n26_ = NAND ( NET_4, NET_3 ) NET_27 = NAND ( new_n26_, new_n25_, new_n22_ ) new_n28_ = NOR ( NET_4, NET_2, NET_1 ) new_n29_ = NOR ( NET_2, new_n23_ ) new_n30_ = NOR ( new_n29_, new_n12_ ) new_n31_ = NOR ( new_n30_, NET_3 ) NET_28 = OR ( new_n31_, new_n28_ ) NET_6 = BUF ( NET_5 ) NET_2313123 = DFF ( NET_5 )