make: 'atpg' is up to date.
========================
parsing file ./benchmark/b01.bench ... Done.
====== Circuit Statistics ====== 
PI:	7
PO:	7
Gate:	48
Stem:	28
Level:	3
================================ 
[SOL] flip: 0, stem: 0, fault:541. flip_cnt: 0, stem_cnt: 28, fault_cnt:42
coverage: 43.750%	pattern: 1	before: 96	now: 54
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:145. flip_cnt: 0, stem_cnt: 28, fault_cnt:39
coverage: 63.542%	pattern: 2	before: 54	now: 35
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:43. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 68.750%	pattern: 3	before: 35	now: 30
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 76.042%	pattern: 4	before: 30	now: 23
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 78.125%	pattern: 5	before: 23	now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 78.125%	pattern: 5	before: 21	now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 78.125%	pattern: 5	before: 21	now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 78.125%	pattern: 5	before: 21	now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 78.125%	pattern: 5	before: 21	now: 21
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:75. flip_cnt: 0, stem_cnt: 28, fault_cnt:32
coverage: 82.292%	pattern: 6	before: 21	now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 82.292%	pattern: 6	before: 17	now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 82.292%	pattern: 6	before: 17	now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 82.292%	pattern: 6	before: 17	now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21
coverage: 82.292%	pattern: 6	before: 17	now: 17
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:49. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 86.458%	pattern: 7	before: 17	now: 13
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 28, fault_cnt:34
coverage: 88.542%	pattern: 8	before: 13	now: 11
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:12. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
coverage: 91.667%	pattern: 9	before: 11	now: 8
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 28, fault_cnt:37
coverage: 94.792%	pattern: 10	before: 8	now: 5
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 95.833%	pattern: 11	before: 5	now: 4
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 96.875%	pattern: 12	before: 4	now: 3
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:31
coverage: 96.875%	pattern: 12	before: 3	now: 3
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 97.917%	pattern: 13	before: 3	now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:38
coverage: 97.917%	pattern: 13	before: 2	now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 28, fault_cnt:28
coverage: 98.958%	pattern: 14	before: 2	now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 28, fault_cnt:34
coverage: 100.000%	pattern: 15	before: 1	now: 0
checking valid circuit ... result: 1.

real	0m0.364s
user	0m0.359s
sys	0m0.004s