make: 'atpg' is up to date. ======================== parsing file ./benchmark/c7552.bench ... Done. ====== Circuit Statistics ====== PI: 207 PO: 108 Gate: 3719 Stem: 1537 Level: 10 ================================ [SOL] flip: 0, stem: 0, fault:31574. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1667 coverage: 22.412% pattern: 1 before: 7438 now: 5771 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:23913. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1701 coverage: 40.656% pattern: 2 before: 5771 now: 4414 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:13051. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1593 coverage: 50.094% pattern: 3 before: 4414 now: 3712 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:5949. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503 coverage: 54.329% pattern: 4 before: 3712 now: 3397 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:6654. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561 coverage: 59.196% pattern: 5 before: 3397 now: 3035 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:4089. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1580 coverage: 62.140% pattern: 6 before: 3035 now: 2816 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:3109. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1443 coverage: 64.372% pattern: 7 before: 2816 now: 2650 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:6042. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1750 coverage: 68.647% pattern: 8 before: 2650 now: 2332 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:4459. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1716 coverage: 71.847% pattern: 9 before: 2332 now: 2094 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:1653. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483 coverage: 73.017% pattern: 10 before: 2094 now: 2007 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:1121. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1430 coverage: 73.810% pattern: 11 before: 2007 now: 1948 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:7467. flip_cnt: 0, stem_cnt: 1537, fault_cnt:2099 coverage: 79.094% pattern: 12 before: 1948 now: 1555 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:950. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1522 coverage: 79.766% pattern: 13 before: 1555 now: 1505 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:950. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1594 coverage: 80.438% pattern: 14 before: 1505 now: 1455 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:1676. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1648 coverage: 81.675% pattern: 15 before: 1455 now: 1363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:951. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561 coverage: 82.361% pattern: 16 before: 1363 now: 1312 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:1634. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1681 coverage: 83.517% pattern: 17 before: 1312 now: 1226 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:741. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1450 coverage: 84.041% pattern: 18 before: 1226 now: 1187 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1442 coverage: 84.136% pattern: 19 before: 1187 now: 1180 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1453 coverage: 84.364% pattern: 20 before: 1180 now: 1163 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:855. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1559 coverage: 84.969% pattern: 21 before: 1163 now: 1118 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:1178. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1681 coverage: 85.803% pattern: 22 before: 1118 now: 1056 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1426 coverage: 85.803% pattern: 22 before: 1056 now: 1056 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:1007. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1759 coverage: 86.515% pattern: 23 before: 1056 now: 1003 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1412 coverage: 86.636% pattern: 24 before: 1003 now: 994 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1487 coverage: 86.650% pattern: 25 before: 994 now: 993 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1565 coverage: 86.959% pattern: 26 before: 993 now: 970 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483 coverage: 86.986% pattern: 27 before: 970 now: 968 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1410 coverage: 87.161% pattern: 28 before: 968 now: 955 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:589. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1582 coverage: 87.577% pattern: 29 before: 955 now: 924 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1482 coverage: 87.591% pattern: 30 before: 924 now: 923 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1508 coverage: 87.927% pattern: 31 before: 923 now: 898 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1509 coverage: 87.981% pattern: 32 before: 898 now: 894 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1609 coverage: 88.196% pattern: 33 before: 894 now: 878 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:456. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494 coverage: 88.518% pattern: 34 before: 878 now: 854 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:1064. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1930 coverage: 89.271% pattern: 35 before: 854 now: 798 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1542 coverage: 89.567% pattern: 36 before: 798 now: 776 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1546 coverage: 89.836% pattern: 37 before: 776 now: 756 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1877 coverage: 90.038% pattern: 38 before: 756 now: 741 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1523 coverage: 90.266% pattern: 39 before: 741 now: 724 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1468 coverage: 90.266% pattern: 39 before: 724 now: 724 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:456. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1836 coverage: 90.589% pattern: 40 before: 724 now: 700 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1527 coverage: 90.643% pattern: 41 before: 700 now: 696 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1632 coverage: 90.925% pattern: 42 before: 696 now: 675 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:741. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1829 coverage: 91.449% pattern: 43 before: 675 now: 636 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1530 coverage: 91.517% pattern: 44 before: 636 now: 631 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1653 coverage: 91.543% pattern: 45 before: 631 now: 629 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1950 coverage: 91.772% pattern: 46 before: 629 now: 612 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503 coverage: 91.812% pattern: 47 before: 612 now: 609 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1534 coverage: 91.853% pattern: 48 before: 609 now: 606 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1537 coverage: 91.960% pattern: 49 before: 606 now: 598 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1579 coverage: 91.974% pattern: 50 before: 598 now: 597 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1551 coverage: 91.974% pattern: 50 before: 597 now: 597 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1645 coverage: 92.001% pattern: 51 before: 597 now: 595 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1465 coverage: 92.001% pattern: 51 before: 595 now: 595 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1585 coverage: 92.108% pattern: 52 before: 595 now: 587 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1862 coverage: 92.135% pattern: 53 before: 587 now: 585 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1505 coverage: 92.202% pattern: 54 before: 585 now: 580 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1486 coverage: 92.283% pattern: 55 before: 580 now: 574 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1435 coverage: 92.283% pattern: 55 before: 574 now: 574 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1423 coverage: 92.350% pattern: 56 before: 574 now: 569 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1763 coverage: 92.404% pattern: 57 before: 569 now: 565 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1868 coverage: 92.511% pattern: 58 before: 565 now: 557 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1436 coverage: 92.511% pattern: 58 before: 557 now: 557 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1419 coverage: 92.511% pattern: 58 before: 557 now: 557 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1666 coverage: 92.525% pattern: 59 before: 557 now: 556 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1564 coverage: 92.552% pattern: 60 before: 556 now: 554 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1516 coverage: 92.606% pattern: 61 before: 554 now: 550 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1655 coverage: 92.673% pattern: 62 before: 550 now: 545 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1607 coverage: 92.673% pattern: 62 before: 545 now: 545 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 1537, fault_cnt:2158 coverage: 93.009% pattern: 63 before: 545 now: 520 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1497 coverage: 93.036% pattern: 64 before: 520 now: 518 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1658 coverage: 93.076% pattern: 65 before: 518 now: 515 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1833 coverage: 93.076% pattern: 65 before: 515 now: 515 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1470 coverage: 93.076% pattern: 65 before: 515 now: 515 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1603 coverage: 93.170% pattern: 66 before: 515 now: 508 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1562 coverage: 93.197% pattern: 67 before: 508 now: 506 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1866 coverage: 93.197% pattern: 67 before: 506 now: 506 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1837 coverage: 93.211% pattern: 68 before: 506 now: 505 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1634 coverage: 93.278% pattern: 69 before: 505 now: 500 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1725 coverage: 93.318% pattern: 70 before: 500 now: 497 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1582 coverage: 93.332% pattern: 71 before: 497 now: 496 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1477 coverage: 93.332% pattern: 71 before: 496 now: 496 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1427 coverage: 93.332% pattern: 71 before: 496 now: 496 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1645 coverage: 93.332% pattern: 71 before: 496 now: 496 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1462 coverage: 93.332% pattern: 71 before: 496 now: 496 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1796 coverage: 93.332% pattern: 71 before: 496 now: 496 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1657 coverage: 93.439% pattern: 72 before: 496 now: 488 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1473 coverage: 93.439% pattern: 72 before: 488 now: 488 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1526 coverage: 93.439% pattern: 72 before: 488 now: 488 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1571 coverage: 93.439% pattern: 72 before: 488 now: 488 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1449 coverage: 93.439% pattern: 72 before: 488 now: 488 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1583 coverage: 93.439% pattern: 72 before: 488 now: 488 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1499 coverage: 93.439% pattern: 72 before: 488 now: 488 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1690 coverage: 93.560% pattern: 73 before: 488 now: 479 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1587 coverage: 93.614% pattern: 74 before: 479 now: 475 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1543 coverage: 93.614% pattern: 74 before: 475 now: 475 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1457 coverage: 93.614% pattern: 74 before: 475 now: 475 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1513 coverage: 93.654% pattern: 75 before: 475 now: 472 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1425 coverage: 93.654% pattern: 75 before: 472 now: 472 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1876 coverage: 93.708% pattern: 76 before: 472 now: 468 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1778 coverage: 93.708% pattern: 76 before: 468 now: 468 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1431 coverage: 93.721% pattern: 77 before: 468 now: 467 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483 coverage: 93.775% pattern: 78 before: 467 now: 463 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1481 coverage: 93.802% pattern: 79 before: 463 now: 461 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1592 coverage: 93.802% pattern: 79 before: 461 now: 461 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1804 coverage: 93.802% pattern: 79 before: 461 now: 461 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1605 coverage: 93.816% pattern: 80 before: 461 now: 460 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1668 coverage: 93.842% pattern: 81 before: 460 now: 458 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1840 coverage: 93.842% pattern: 81 before: 458 now: 458 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1441 coverage: 93.842% pattern: 81 before: 458 now: 458 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1662 coverage: 93.869% pattern: 82 before: 458 now: 456 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1452 coverage: 93.869% pattern: 82 before: 456 now: 456 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1448 coverage: 93.869% pattern: 82 before: 456 now: 456 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1592 coverage: 93.869% pattern: 82 before: 456 now: 456 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1529 coverage: 93.869% pattern: 82 before: 456 now: 456 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1575 coverage: 93.896% pattern: 83 before: 456 now: 454 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1555 coverage: 93.896% pattern: 83 before: 454 now: 454 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503 coverage: 93.896% pattern: 83 before: 454 now: 454 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1606 coverage: 93.896% pattern: 83 before: 454 now: 454 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1529 coverage: 93.923% pattern: 84 before: 454 now: 452 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1572 coverage: 93.923% pattern: 84 before: 452 now: 452 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1506 coverage: 93.923% pattern: 84 before: 452 now: 452 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1544 coverage: 94.152% pattern: 85 before: 452 now: 435 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1441 coverage: 94.152% pattern: 85 before: 435 now: 435 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1487 coverage: 94.152% pattern: 85 before: 435 now: 435 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1572 coverage: 94.152% pattern: 85 before: 435 now: 435 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1944 coverage: 94.367% pattern: 86 before: 435 now: 419 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1555 coverage: 94.367% pattern: 86 before: 419 now: 419 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1453 coverage: 94.367% pattern: 86 before: 419 now: 419 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1828 coverage: 94.367% pattern: 86 before: 419 now: 419 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1570 coverage: 94.407% pattern: 87 before: 419 now: 416 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1760 coverage: 94.434% pattern: 88 before: 416 now: 414 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1478 coverage: 94.434% pattern: 88 before: 414 now: 414 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1486 coverage: 94.434% pattern: 88 before: 414 now: 414 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1478 coverage: 94.474% pattern: 89 before: 414 now: 411 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1512 coverage: 94.474% pattern: 89 before: 411 now: 411 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1463 coverage: 94.474% pattern: 89 before: 411 now: 411 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1469 coverage: 94.474% pattern: 89 before: 411 now: 411 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1621 coverage: 94.474% pattern: 89 before: 411 now: 411 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1658 coverage: 94.474% pattern: 89 before: 411 now: 411 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1428 coverage: 94.474% pattern: 89 before: 411 now: 411 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1568 coverage: 94.474% pattern: 89 before: 411 now: 411 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1868 coverage: 94.474% pattern: 89 before: 411 now: 411 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1593 coverage: 94.568% pattern: 90 before: 411 now: 404 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1520 coverage: 94.568% pattern: 90 before: 404 now: 404 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1638 coverage: 94.568% pattern: 90 before: 404 now: 404 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1527 coverage: 94.568% pattern: 90 before: 404 now: 404 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1458 coverage: 94.568% pattern: 90 before: 404 now: 404 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1534 coverage: 94.568% pattern: 90 before: 404 now: 404 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1876 coverage: 94.568% pattern: 90 before: 404 now: 404 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561 coverage: 94.568% pattern: 90 before: 404 now: 404 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1502 coverage: 94.595% pattern: 91 before: 404 now: 402 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1616 coverage: 94.595% pattern: 91 before: 402 now: 402 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494 coverage: 94.622% pattern: 92 before: 402 now: 400 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1868 coverage: 94.622% pattern: 92 before: 400 now: 400 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1746 coverage: 94.622% pattern: 92 before: 400 now: 400 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1537 coverage: 94.622% pattern: 92 before: 400 now: 400 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1514 coverage: 94.622% pattern: 92 before: 400 now: 400 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1484 coverage: 94.622% pattern: 92 before: 400 now: 400 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1627 coverage: 94.622% pattern: 92 before: 400 now: 400 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1566 coverage: 94.649% pattern: 93 before: 400 now: 398 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1472 coverage: 94.649% pattern: 93 before: 398 now: 398 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1931 coverage: 94.824% pattern: 94 before: 398 now: 385 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1464 coverage: 94.824% pattern: 94 before: 385 now: 385 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1535 coverage: 94.824% pattern: 94 before: 385 now: 385 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1591 coverage: 94.824% pattern: 94 before: 385 now: 385 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1606 coverage: 94.824% pattern: 94 before: 385 now: 385 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1452 coverage: 94.824% pattern: 94 before: 385 now: 385 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1820 coverage: 94.851% pattern: 95 before: 385 now: 383 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1717 coverage: 94.864% pattern: 96 before: 383 now: 382 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1742 coverage: 94.878% pattern: 97 before: 382 now: 381 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1474 coverage: 94.878% pattern: 97 before: 381 now: 381 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1878 coverage: 94.878% pattern: 97 before: 381 now: 381 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1513 coverage: 94.878% pattern: 97 before: 381 now: 381 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1577 coverage: 94.878% pattern: 97 before: 381 now: 381 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1897 coverage: 94.878% pattern: 97 before: 381 now: 381 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1576 coverage: 94.878% pattern: 97 before: 381 now: 381 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483 coverage: 94.878% pattern: 97 before: 381 now: 381 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1607 coverage: 94.878% pattern: 97 before: 381 now: 381 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1473 coverage: 94.878% pattern: 97 before: 381 now: 381 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1543 coverage: 94.905% pattern: 98 before: 381 now: 379 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1482 coverage: 94.905% pattern: 98 before: 379 now: 379 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1465 coverage: 94.905% pattern: 98 before: 379 now: 379 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1910 coverage: 95.066% pattern: 99 before: 379 now: 367 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1437 coverage: 95.066% pattern: 99 before: 367 now: 367 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1698 coverage: 95.066% pattern: 99 before: 367 now: 367 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1495 coverage: 95.079% pattern: 100 before: 367 now: 366 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1419 coverage: 95.079% pattern: 100 before: 366 now: 366 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1550 coverage: 95.079% pattern: 100 before: 366 now: 366 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1826 coverage: 95.079% pattern: 100 before: 366 now: 366 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1712 coverage: 95.079% pattern: 100 before: 366 now: 366 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573 coverage: 95.079% pattern: 100 before: 366 now: 366 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1492 coverage: 95.106% pattern: 101 before: 366 now: 364 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1869 coverage: 95.106% pattern: 101 before: 364 now: 364 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1499 coverage: 95.106% pattern: 101 before: 364 now: 364 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1529 coverage: 95.106% pattern: 101 before: 364 now: 364 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1510 coverage: 95.106% pattern: 101 before: 364 now: 364 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1578 coverage: 95.106% pattern: 101 before: 364 now: 364 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1878 coverage: 95.106% pattern: 101 before: 364 now: 364 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1470 coverage: 95.106% pattern: 101 before: 364 now: 364 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1563 coverage: 95.106% pattern: 101 before: 364 now: 364 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1637 coverage: 95.120% pattern: 102 before: 364 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1444 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1551 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1945 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1623 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1684 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1539 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1519 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1463 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1579 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1409 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1512 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1836 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1556 coverage: 95.120% pattern: 102 before: 363 now: 363 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1646 coverage: 95.133% pattern: 103 before: 363 now: 362 checking valid circuit ... result: 1. [SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1527 coverage: 95.133% pattern: 103 before: 362 now: 362 checking valid circuit ... result: 1.