atpg-ls/exp_result/ATPG-LS_b06.bench.txt
2023-03-09 14:54:23 +08:00

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make: 'atpg' is up to date.
========================
parsing file ./benchmark/b06.bench ... Done.
====== Circuit Statistics ======
PI: 11
PO: 15
Gate: 56
Stem: 42
Level: 3
================================
[SOL] flip: 0, stem: 0, fault:159. flip_cnt: 0, stem_cnt: 42, fault_cnt:43
coverage: 38.393% pattern: 1 before: 112 now: 69
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:107. flip_cnt: 0, stem_cnt: 42, fault_cnt:43
coverage: 65.179% pattern: 2 before: 69 now: 39
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:23. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
coverage: 78.571% pattern: 3 before: 39 now: 24
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:64. flip_cnt: 0, stem_cnt: 42, fault_cnt:46
coverage: 90.179% pattern: 4 before: 24 now: 11
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 42, fault_cnt:41
coverage: 91.071% pattern: 5 before: 11 now: 10
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:54. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
coverage: 94.643% pattern: 6 before: 10 now: 6
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 42, fault_cnt:36
coverage: 97.321% pattern: 7 before: 6 now: 3
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:14. flip_cnt: 0, stem_cnt: 42, fault_cnt:43
coverage: 98.214% pattern: 8 before: 3 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:40
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:34
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:46
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:45
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:35
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:36
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:41
coverage: 98.214% pattern: 8 before: 2 now: 2
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 42, fault_cnt:47
coverage: 99.107% pattern: 9 before: 2 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:41
coverage: 99.107% pattern: 9 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:46
coverage: 99.107% pattern: 9 before: 1 now: 1
checking valid circuit ... result: 1.
[SOL] flip: 0, stem: 0, fault:15. flip_cnt: 0, stem_cnt: 42, fault_cnt:44
coverage: 100.000% pattern: 10 before: 1 now: 0
checking valid circuit ... result: 1.
real 0m0.107s
user 0m0.105s
sys 0m0.000s