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YuhangQ d519dd68d4 upload(experiment): 生成了 verilog
2024-12-04 08:58:48 +00:00
experiment
upload(experiment): 生成了 verilog
2024-12-04 08:58:48 +00:00
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README.md
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README.md

demiter

将 AIG 的 miter 电路划分成两个电路

Description
使用商业工具测试 AIG 格式的 miter 电路等价性
Readme 16 MiB
Languages
Coq 87.4%
Verilog 9.2%
V 2.3%
Python 1.1%