29 lines
1.2 KiB (Stored with Git LFS)
Verilog

// Benchmark "demiter_aig/TOP1_2" written by ABC on Wed Dec 4 08:51:46 2024
module \demiter_aig/TOP1_2 (
pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, pi10, pi11,
pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, pi20, pi21, pi22, pi23,
pi24, pi25, pi26, pi27, pi28, pi29, pi30, pi31, pi32, pi33, pi34, pi35,
pi36, pi37, pi38, pi39, pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47,
po0 );
input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, pi20, pi21,
pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, pi30, pi31, pi32, pi33,
pi34, pi35, pi36, pi37, pi38, pi39, pi40, pi41, pi42, pi43, pi44, pi45,
pi46, pi47;
output po0;
wire new_n50_, new_n51_, new_n52_, new_n53_, new_n54_, new_n55_, new_n56_,
new_n57_;
assign new_n50_ = pi12 & pi21;
assign new_n51_ = pi27 & pi28;
assign new_n52_ = pi04 & pi17;
assign new_n53_ = new_n51_ & ~new_n52_;
assign new_n54_ = ~new_n51_ & new_n52_;
assign new_n55_ = ~new_n53_ & ~new_n54_;
assign new_n56_ = ~new_n50_ & ~new_n55_;
assign new_n57_ = new_n50_ & new_n55_;
assign po0 = new_n56_ | new_n57_;
endmodule